I can't seem to find the explanation for why RW stage of a single cycle processor takes the shortest time to execute. Can anybody explain why this is so.

  • $\begingroup$ This is indeed a quite odd assertion. Maybe your lecture uses as reference an architecture where almost nothing remains to do in this phase, some CPUs manage cache read back, exceptions... during the write stage which makes it a bit complex. $\endgroup$
    – TEMLIB
    Apr 23 '20 at 12:04
  • $\begingroup$ Maybe it's related to some operations which can take several cycles (instruction fetch, memory read, memory write, integer division...), while register write is always only one cycle long. $\endgroup$
    – TEMLIB
    Apr 23 '20 at 12:06

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