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How does having separate instruction and data memories help in implementing a single cycle datapath for a MIPS instruction set? I want to know why we can only use a datapath element once in a cycle for making the datapath capable of executing any instruction in a single cycle.

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Each element in that data path is purely logical, thus in each cycle an element can perform only a single operation. If you had only one memory element, you would've possibly need to perform two operations in one cycle: (1) read the instruction (2) read/write data. This is impossible with a logic-only (sateless) elements within a single cycle.

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  • $\begingroup$ i think memory is a state element $\endgroup$ May 10, 2020 at 15:46

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