How does a cache handle overwriting between 2 addresses in the same block?

Question

Consider a byte-addressable cache with block size 16 bytes, bytes 0-15 form one block. First I write an int(let's say 7) to address 0, so now bytes 0-3 contain the int 7. Now if I try to write another int(9) to address 2, then how does the cache handle this? Also if i try to read from byte 1, what effect does that have?

The lectures I'm watching suggest treating a block as the atomic unit in a cache, because keeping track of all the unwritten and written bytes will be a resource heavy task. So how will the above situation pan out? Will every block contain only 1 instance of data, with every write beginning from byte 0? because that is the only possible solution i can think of.

Answer 1

Your program will work exactly as if there was no cache, and as if each single memory operation was completed before the next one is started.

Typical implementations will first make sure that the complete data for a cache line is stored in the cache. So for example writing four bytes may first read the complete 64 byte line from memory.

With a line of data in cache, accessing it can be done very quickly. If there are multiple instructions reading or writing, you can expect one to be executed completely in each cycle. If instructions access different cache lines, a powerful processor may allow simultaneous access to two different cache lines. A powerful processor may also allow simultaneous access to clearly separate parts of a cache line. 4 bytes at location 2 and 4 bytes at location 6 may not count as “clearly” separate.

If you access different cache lines, the one that is accessed by a later instruction may be available in the cache earlier, and the actual access may happen earlier.

Answer 2

The lectures I'm watching suggest treating a block as the atomic unit in a cache

This is true when you are writing the contents of a cache block back to memory. However, when you write to a cache block, you usually only overwrite part of it (x86 has 64-byte cache blocks). You can assume the cache writes are similar to memory writes.

... how does the cache handle this?

This is implementation-specific. When you do two back-to-back STORE_WORD instructions, say storing 7 and 9 to address 0x0 and 0x2 respectively (this is forbidden on many platforms like ARM because your memory accesses are not alligned), a cpu may just do two writes, while some other cpu may do the overwritting internally and only one write to the cache. You can argue that the latter probably will never happen because it increases hardware complexity without much performance gain, but in theory some one can do this.

... if i try to read from byte 1, what effect does that have?

You will get the "correct value", i.e. the byte from the first-written 7. This is because your program SPECIFIES the behavior. In other words, the second write must happen at least effectively after the first write has finished. How the processor manages the cache is implementation detail and no matter how it is implemented, you should see the behavior defined by the ISA.