Suppose a new, more complicated, instruction is desired for this simple pipelined MIPS processor. Suppose, also, it could be implemented by either (a) adding new logic to the execute stage of the pipeline, or (b) adding a new stage (i.e a 6th stage) altogether. Assume that choice (a) would slow the execute stage down by 20%. Since choice (b) increases the number of stages by 20%, is the overall effect on execution the same? If not, describe how each choice affects execution time and indicate which choice is better.
This was a question in my exam, but I'm not sure if my answer to it is correct. Here is what I think:
If the execution stage time increased by 20%, then the new cycle time will likely be the time of the execution stage. So cycle time will increase by 20%.
Adding a new stage to the pipeline wouldn't affect the cycle time (assuming the new stage is shorter than or equal to the longest stage). It would increase the throughput, but also increase the latency of individual instructions by 20%.
So, no, they don't have the same affect on overall performance. The second choice is more efficient.
Now, am I correct?