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Suppose a new, more complicated, instruction is desired for this simple pipelined MIPS processor. Suppose, also, it could be implemented by either (a) adding new logic to the execute stage of the pipeline, or (b) adding a new stage (i.e a 6th stage) altogether. Assume that choice (a) would slow the execute stage down by 20%. Since choice (b) increases the number of stages by 20%, is the overall effect on execution the same? If not, describe how each choice affects execution time and indicate which choice is better.

This was a question in my exam, but I'm not sure if my answer to it is correct. Here is what I think:

If the execution stage time increased by 20%, then the new cycle time will likely be the time of the execution stage. So cycle time will increase by 20%.

Adding a new stage to the pipeline wouldn't affect the cycle time (assuming the new stage is shorter than or equal to the longest stage). It would increase the throughput, but also increase the latency of individual instructions by 20%.

So, no, they don't have the same affect on overall performance. The second choice is more efficient.

Now, am I correct?

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  • $\begingroup$ We discourage "please check my answer" questions, as they only allow for yes or no answers, which are unlikely to be useful to others in the future. $\endgroup$ – D.W. Jun 5 '20 at 23:07
  • $\begingroup$ Should I delete it, then? $\endgroup$ – lostperson Jun 5 '20 at 23:10
  • $\begingroup$ It's not required, but I want you to be aware that you might not get an answer, and to encourage you to think about your questions from that perspective in the future. What prevents you from answering yourself? If there is some concept you don't understand, perhaps you can figure out a useful question to ask about that concept, and that'll be useful to everyone who is studying that concept. $\endgroup$ – D.W. Jun 6 '20 at 1:43
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Your answer is probably correct for an exam.

In reality, adding a pipeline stage to MIPS is a major undertaking. The MIPS pipeline is very simple, that’s why it is taught in CS courses. Adding a pipeline stage adds a whole new level of complexity. Take an instruction sequence

X = A+B
X = C+D
Z = X+Y

In the current pipeline design, Z can just about be made to pick up the correct X - when C+D is stored, it goes directly into the first input of X+Y. With an additional pipeline stage, the second X is nowhere near ready when the third instruction starts. So you must make that instruction wait. But only because X isn’t ready in time. Since you don’t want to always wait, you need to detect this and add logic for that. And then the question is how often does this happen.

The alternative is that instructions using the second pipeline stage - and only those - stop all the other stages from progressing. So the timing would be the same as if this instruction was two instructions. In that case you could just make it two instructions.

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