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After instruction has been fetched, does it go to control unit and register file at the same time or one after the other? For example if the control unit and register read both have 80ps delay, and we're calculating the total delay for a cycle, would we take their delay as 80ps(if they occur simultaneously) or if they happen one after the other so in that case delay of decode and operand fetch would be 160ps. Which one is correct?

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    $\begingroup$ Please decide if you mean ps or ns. $\endgroup$ – gnasher729 Jul 5 at 9:49
  • $\begingroup$ wrote ns by mistake! its ps $\endgroup$ – Miza Jul 5 at 12:13
  • $\begingroup$ Please edit the question - don't just leave clarifications in the comments. $\endgroup$ – D.W. Aug 4 at 16:51
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Figured it out. The control unit and register file are accessed one after the other. So the total delay would be 160ps.

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