The pipeline of a modern processor has many stages that may issue read requests to main memory, e.g. in fetching the next command or loading some memory location into a register. How is the result of a read request returned to the right pipeline stage, given that there are more than one possible recipients? Since most CPUs access main memory via a cache hierarchy, the question becomes: how does the L1 cache know which part of the pipeline to return a result to?
I imagine that access to the L1 cache is queued, but each access presumably needs a 'return address'. How is this typically handled?
Processors tend to have a LSU (= load-store unit), see [1, 2] for example, but those descriptions tend not to mention how read data finds its recipient.