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The pipeline of a modern processor has many stages that may issue read requests to main memory, e.g. in fetching the next command or loading some memory location into a register. How is the result of a read request returned to the right pipeline stage, given that there are more than one possible recipients? Since most CPUs access main memory via a cache hierarchy, the question becomes: how does the L1 cache know which part of the pipeline to return a result to?

I imagine that access to the L1 cache is queued, but each access presumably needs a 'return address'. How is this typically handled?

Processors tend to have a LSU (= load-store unit), see [1, 2] for example, but those descriptions tend not to mention how read data finds its recipient.

  1. RISC-V Boom, The Load/Store Unit (LSU).

  2. Arm, Load Store Unit (LSU).

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Every machine instruction encodes the source and destination registers and/or memory locations. For memory location, some temporary buffer (register) within the processor is used. If the memory location happened to be in the cache, the stage of pipeline which depends on the content of memory location, stalls for few cycles.

Also, there are buffer registers between every pipeline stage, that stores the input for next stage and output of previous stage. If the processor is superscalar, i.e., multiple instructions can be in flight at a certain point of time, then multiple copies of buffers are maintained. Since the instruction can be executed Out-of-Order on superscalar processors, buffers like ROB (re-order buffers) are maintained for every hardware (SMT) threads. Put simply, multiple register sets which are copies of processor register sets are maintained within a processor.

In other words, Control unit that control the instruction execution cycles, appropriately route the content of memory location to marked registers. Registers are either specified by instruction code or determined by control unit itself.

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  • $\begingroup$ By the time the pipeline is in action, the machine instructions are decomposed, so the control unit will somehow have to remember where each reply to a read request will have to go to, right? $\endgroup$
    – Martin Berger
    Aug 3, 2020 at 9:52
  • $\begingroup$ Decode stage(s) follow fetch stage(s). During decode, from the machine code of instruction itself, it is clear where to get the source operand from and where to store the output. If operand locations are registers, the instruction specifies the locations. if they are memory location, some temporary buffer is used within the processor. Memory management unit takes over from there to appropriately route it to mentioned memory locations. $\endgroup$
    – ajit
    Aug 3, 2020 at 11:32
  • $\begingroup$ Yes, it is clear from the machine command and the micro-architecture where the result of a read should go. I am just wondering how this is is implemented in practise. For example a read-request to the dRAM could include an explicit return address (as it would be in the TCP/IP network stack), in this case the LSU does not need do remember where to route a returned read value, it could just look at the data. OTOH, if the request does not have a return address, this needs to be accounted for in the LSU / control unit. $\endgroup$
    – Martin Berger
    Aug 3, 2020 at 12:40
  • $\begingroup$ Did you mean by "explicit return address" - "a location in processor, say a specific register"? $\endgroup$
    – ajit
    Aug 4, 2020 at 1:02
  • $\begingroup$ Yes! A read request is made so the value read needs to go to some part of the pipeline, e.g. the Fetch unit needs the value of the PC and then the value of the memory location pointed to by the PC. $\endgroup$
    – Martin Berger
    Aug 4, 2020 at 8:37

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