I am having some confusion between address bus size, physical address size and word size however (I do understand that unit of memory access is word and when word size is one byte then it's known as byte-addressable).

  • $\begingroup$ I hope address bus size is same as physical address size. But there is no such constrain for the word size to be equal to the address bus size / physical address size.. But 1 thing is for sure. The address bus width should be less than the word length of the system. If it is not then the extra address bus width is of no use and that memory remains unused I hope.suppose you have a 32 bit system. Then the highest memory location address your memory can hold is 32 bit which is equivalent to a $2^{32}$ bytes memory in byte addressable system or $2^{32}\times 4$ bytes if the system is word addr $\endgroup$ – Abhishek Ghosh Aug 2 '20 at 6:36
  • $\begingroup$ I appreciate your effort, but honestly I don't think my question was fully answered, I'd like to get bit more clarification on crux of the question. $\endgroup$ – Pawan Nirpal Aug 2 '20 at 7:23
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    $\begingroup$ @AbhishekGhosh: I think it is quite common, especially for "ridiculously large" address sizes such as 64 bit or even 128 bit, it is quite common that the physical address size is smaller. E.g. neither the current AMD nor Intel processors actually have 64 address pins. I think they are somewhere in the high 50s at the moment. $\endgroup$ – Jörg W Mittag Aug 2 '20 at 11:48

Is address bus size same as physical address size

No, not necessarily. Especially with modern 64 bit address bus sizes, it is quite common that CPUs do not actually support 64 bit physical addresses.

For example, the first AMD64 CPUs had 40 bit physical addresses, the current ones have 48 bit. In fact, due to the Page Table Entry format, physical addresses cannot be larger than 52 bit.

and is that the same as word size?

No, not necessarily. It makes stuff easier, but there have been architectures where the bus was half the word size, and you had to transmit a word in two bus cycles. Conversely, it is also possible to have the bus width be an integer multiple of the word size, making it possible to transmit multiple words per bus cycle.

Just as an example: the IBM 704, one of the most famous computers of all time (both FORTRAN and LISP were first implemented for the IBM 704, the trajectory data for Gemini and Apollo was computed on one) has 36 bit words but 15 bit addresses.

  • $\begingroup$ Well what's the use then, as you said it doesn't make data movement efficient then, or they have a word equal to byte only then it would make sense to get multiple words in one bus cycle. $\endgroup$ – Pawan Nirpal Aug 2 '20 at 12:51

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