In simple CPU architectures, such as the one discussed here https://youtu.be/zltgXvg6r3k?t=109, an instruction loaded from RAM is executed exactly one clock cycle after it is loaded into the instruction register. This fact is key to the whole architecture working.
However, I am told that in real/modern architectures it takes hundreds of clock cycles to fetch instructions from RAM (using caches in between). But that completely throws off my understanding of how things work. I am told that often or ultimately the CPU has to undergo "pipeline stall", but I can't find any schematic description of how stalling works, or how the CPU is signaled to re-commence once the instruction from RAM has been fetched at some indeterminate number of future clock cycles.
Could someone please outline the techniques/processes that enable instructions ordered from RAM to get executed after some indefinite number of clock cycles in the future?