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I understand that computer memory data is sequential;
It is one long line organized in one or more address/es, each of which containing one or more fixed size word/s which contain raw data (in an initial manner, just offset value/s, I would assume).

Why does memory data isn't organized in two or more lines (why it's just one long line, or at least, so it would appear, via a user interface such as some text editor)?

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    $\begingroup$ What do you intend to gain by splitting it into multiple lines? And I doubt that an actual RAM is physically represented as a linear sequence of memory cells. $\endgroup$
    – user114966
    Aug 14, 2020 at 16:28
  • $\begingroup$ Sorry, I don't understand what you are talking about in your comment at all. $\endgroup$
    – user114966
    Aug 14, 2020 at 16:53
  • $\begingroup$ @Dmitry if someone edits that machine code it will likely be easier (if it would at all be easy) to edit code organized in lines instead just one long line; that's the gain... $\endgroup$
    – George
    Aug 14, 2020 at 17:47

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The notion of a "line" is an abstraction we impose. Currently our memory works as follows: you provide an address to the memory module that you want to read, and it returns the value at that address; or if you want to update memory, you provide an address and the new value, and it overwrites the value at that address with the new value.

Why do we build memory that way? Well, the current way is simple and works, and can be implemented efficiently in circuits. If you wanted to consider some other alternative, you'd have to think about what are the benefits and what are the costs. I'm not clear on exactly how your counter-proposal would work, but I expect it would add complexity (which ultimately might add to the cost of implement the memory subsystem, and also might make the system harder to understand for programmers) without a benefit that would make it worthwhile. If you wanted to dive into this in more detail, you'd probably start by learning how RAM works at the circuit level. Our current RAM is highly optimized to minimize the number of gates needed, i.e., to minimize cost.

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