# Multi-level paging where the inner level page tables are split into pages with entries occupying half the page size

A processor uses $$36$$ bit physical address and $$32$$ bit virtual addresses, with a page frame size of $$4$$ Kbytes. Each page table entry is of size $$4$$ bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows:

• Bits $$30-31$$ are used to index into the first level page table.
• Bits $$21-29$$ are used to index into the 2nd level page table.
• Bits $$12-20$$ are used to index into the 3rd level page table.
• Bits $$0-11$$ are used as offset within the page.

The number of bits required for addressing the next level page table(or page frame) in the page table entry of the first, second and third level page tables are respectively

(a) $$\text{20,20,20}$$

(b) $$\text{24,24,24}$$

(c) $$\text{24,24,20}$$

(d) $$\text{25,25,24}$$

I got the answer as (b) as in each page table we are after all required to point to a frame number in the main memory for the base address.

But in this site here it says that the answer is (d) and the logic which they use of working in chunks of $$2^{11} B$$ I feel ruins or does not go in with the entire concept of paging. Why the system shall suddenly start storing data in main memory in chucks other than the granularity defined by the page size of frame size. I do not get it .

• please can any one help, I still could not find an answer to this on my own – user119726 Jan 10 at 8:36