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Regarding Processor Direct Cache, what is the proper mathematical technique for discovering how many words are loaded on a cache miss?

For example if you have a direct mapped cache with a total data cache size of 32 words and a direct mapped cache of 4-word blocks. I believe I have a cache index of 8 cache blocks:

32/4 = 8

Example: Finding a block in python:

var1 = 56
print ((var1 / 8)% 8)

The answer: 7

So finding where to store the blocks is simple enough but I'm uncertain on a miss exactly how MANY words will be loaded?

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In a typical cache design an entire block is loaded (in your example 4 words). While it is possible to include separate valid bits for smaller chunks (sometimes called sectors, though Intel uses sector to designate the larger group and line for the smaller unit), making it unnecessary to load the entire block, even in that case typically the entire block is loaded on a miss.

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  • $\begingroup$ Having several valid bits per line is also sometimes called "cache sub-blocking". $\endgroup$ – TEMLIB Feb 26 '15 at 2:17

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