When calculating the throughput of a CPU, how does it differ when it is implemented with a single cycle datapath versus a multicycle datapath? If for example the CPU is running 1 GHz freq, then obviously it would have 1,000,000,000 clock cycles per second...and in a single cycle, it takes 1 CPI. So what would be the throughput? And how would it be different in the multicycle datapath where clock cycles differ between instructions?
Every instruction in a CPU goes through an Instruction execution cycle. In other words every instruction goes through multiple stages like Fetch,Decode,Execute,Writeresult. In modern processor the number of stages can go up to 20. So for single cycle instruction execution (all stages finish their work), the clock duration need to be large and hence the processor should operate at lower frequencies. CPI would be 1 and hence throughput is 1/F, where F is processors clock frequency.
But most modern processors use pipelining. They take advantage of the fact that each stage hardware is different and therefore multiple instructions can be at different stages of instruction execution cycle, at the same time. The clock frequency can be higher as amount of work being done (Max of all stage execution time) is smaller. The performance will be optimal if all stages of instruction execution cycle take equal amount of time. Hence a pipelined processor with n stage is able to provide a throughput of one instruction per cycle. CPI should be P where P is the number of pipeline stages. But often a pipeline get stalled and different types of instructions (integer,float, branch, load,store...) take different number of cycles to complete. Hence CPI will vary for each program depending on instruction mix.
Pipelined processor having superscalar execution capabilities are able to take advantage of the fact that there are multiple processing/execution hardware in a processor, e.g., Integer ALU, floating-point ALU, memory management unit. So taking advantage of this fact more than one instruction can be in its execution stage at the same time. To support this fetch and decode stages have the capability to read and process multiple instruction in parallel. They are then able to feed multiple instruction to the execute stage, and more than one instruction is then completed per cycle. CPI will be lower in this case, even going to a value less than 1. In other words more than one instruction is able to complete within a single cycle.