I have consulted many textbooks (Morris Mano, H.P Hayes, Hamacher, William Stallings) but could not find a standard and clear hardware implementation of each of the models of cache organization. It is quite necessary for me to know the logic diagrams of how the comparators, multiplexers and the decoders are used to actually the bring the concept into action. Each textbooks explain the concepts only theoretically with an example, but the actual way the work is done in the hardware is not given. Moreover in few competitive examinations the latencies of various building blocks like MUX, comparators are given and one is asked to find the hit latency. Now without the proper knowledge of the hardware logic diagram, it is quite difficult to answer such questions.

Could anyone explain me the hardware implementation of the each of the 3 types of cache organization. Does there exit a standard design for each of the following?


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