I have the following question:
We begin with a computer implemented in single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of time. The original machine had a clock cycle time of 7 ns. After the stages were split, the measured times were IF, 1 ns; ID, 1.5 ns; EX, 1 ns; MEM, 2 ns; and WB, 1.5 ns. The pipeline register delay is 0.1 ns.
If the pipelined machine had an infinite number of stages, what would its speedup be over the single-cycle machine?
I have no idea how to approach this question, any help or hints would be appreciated.
I thought that I might be able to use (time per instruction without pipeline)/(number of stages) since the stages will all have 2.1 ns reserved but it obviously seems 0 which seemed odd to me.