Calculating the pipeline speed up in case we have an infinite amount of stages

Question

I have the following question:

We begin with a computer implemented in single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of time. The original machine had a clock cycle time of 7 ns. After the stages were split, the measured times were IF, 1 ns; ID, 1.5 ns; EX, 1 ns; MEM, 2 ns; and WB, 1.5 ns. The pipeline register delay is 0.1 ns.

If the pipelined machine had an infinite number of stages, what would its speedup be over the single-cycle machine?

I have no idea how to approach this question, any help or hints would be appreciated.

I thought that I might be able to use (time per instruction without pipeline)/(number of stages) since the stages will all have 2.1 ns reserved but it obviously seems 0 which seemed odd to me.

Answer 1

The cycle time/clock period is equal to the time doing actual work plus the overhead (represented, simplistically, as "pipeline register delay" in this problem). The time doing actual work can be approximated as the total time doing actual work divided by the number of stages, so the limit of time doing actual work as the number of stages approaches infinity would be zero. (Pipeline stage imbalance does not matter with infinitesimally short work times.) The clock period can, therefore, be reduced to the pipeline register delay (0.1 ns).

Of course, a slightly more realistic perspective would recognize that work time is quantized (e.g., the time for one level of transistor switching).

This pipeline speed up also only applies to the clock period/frequency not performance. (Also, an infinite pipeline would never complete the first instruction — unless perhaps one had a higher order infinity of time, as pipeline depth would presumably be countably infinite like the integers.☺)

Presumably the problem is only trying to make the student realize that pipeline overhead is a fundamental limit to clock period.