# Harvard processor structure

In my books it is written that the concept of pipelining can happen only with Harvard structure as CPU can both fetch data from and write back data to memory at the same time my question is how can fetching and writing back be done at the same time when there is only one bus for data just like von Neumann structure? How can using an instruction bus be helpful when it only carries instruction but not data?

So if I want to add 2+5 here 2 and 5 are data but + would be the instruction right?

If I fetch 2 and 5 from data cache and add from instruction cache then execute and again write back the result 7 which would be a data to memory and before the whole process is done fetch another data for example 7 and 6 like in what the book stated according to the picture would it still be fetching (the data 7 and 6) and rewriting the data 7 (result of execution) happen at the same time both these numbers are data and have to be fetched and rewritten using data bus so it still be impossible to fetch and rewrite them at the same time and the instruction bus wouldn't be useful.

This is one of the reasons why most modern general-purpose CPUs have split L1 caches, one for instructions and one for data. (It's not the only reason, of course.)

You see, modern CPU pipelines don't interact with a von Neumann-type bus at all, but directly with cache. As far as the pipeline is concerned, instruction memory and data memory are separate because the caches are separate.

Instruction execution cycle have multiple stages like fetch, decode, execute, write back. An instruction execute in multiple clock cycles (separate one for each stage). In pipelined execution multiple instructions are using different stages. Fetch stage access memory to get instructions. Other stages access memory to load and store operands. If there is a single bus connecting the processor to memory either fetch stage can complete or any of the other stage that access the memory to load /store operands (data). If there is a separate bus for instruction and data (or separate cache for instruction and data), both fetch and other stage that access memory for operands(data) can proceed. It is not necessary that every instruction access memory, while being decoded, executed or writing back the result, but some instruction will always be fetched by the fetch stage in every cycle. Presence of split L1 cache for instructions and data is akin to having a Harvard architecture. Even though there is a single bus connecting processor and memory(Von-neumann architecture).

Pipeline stalls are avoided by using Harvard architecture.

"2+5" will take multiple cycles, even multiple instruction to execute. On x86 a simple program will be

//two variable to store data

var1 db 2
var2 dw 5

// program
mov ax,[var1]
mov [sum],ax   // where sum is a memory location.


So there are three instructions. Say you have 3 stage pipeline Fetch,Decode and Execute. Then every instruction will go through 3 stages in 3 clock cycles. Separate cache for instruction and data will ensure that while Instruction 1 is loading the value of var1 in execute stage using the bus connecting data cache, instruction 3 can be fetched using the bus connecting the instruction cache.