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I am given with this information:

"CMP OP1,OP2 will compare registers OP1 and OP2 if they are equal, flag values will be ZF=1, CF=0, if the first operands value is greater flag values will be ZF=0, CF=0, if the first operands value is less than the second operand flag values will be ZF=0,CF=1."

I need to design instruction set architecture for this compare operation but I couldn't understand how to add ZF and CF values inside CMP instruction

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  • $\begingroup$ What do you mean by "design instruction set architecture" in this context? Why do you think you need to add ZF and CF? $\endgroup$
    – D.W.
    Dec 20, 2020 at 20:48
  • $\begingroup$ @dw I think that by "add" they meant "also include", "implement". They didn't mean "sum" $\endgroup$
    – melfnt
    Dec 22, 2020 at 15:33
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    $\begingroup$ @melfnt exactly, I meant 'include'. $\endgroup$
    – Leva
    Dec 23, 2020 at 9:47
  • $\begingroup$ @D.W. by instruction set architecture I mean this :images.app.goo.gl/GzNvYToNDEfd2jfu9 $\endgroup$
    – Leva
    Dec 23, 2020 at 9:48

2 Answers 2

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It's not entirely clear to me what you need to design. You seem to have quoted a part of a description of a ready ISA.

In your description the CMP instruction takes two arguments, i.e. the two registers to be compared. The instruction sets two 1 bit registers or flags based on the outcome of the comparison. These flags don't have to be explicitly given to the CMP instruction because CMP always sets these same registers. After these flags have been set according to the comparison you can use a conditional jump instruction that uses these flags.

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ZF and CF are computed by the instruction and stored in some "status register". They can later be used by conditional jumps. ZF is the "zero" flag and CF the "less than" flag. They can be obtained as a by-product of the subtraction of the two operands.

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