A CPU has a cache with block size $64$ bytes. The main memory has $k$ banks, each bank being $c$ bytes wide. Consecutive $c$ − byte chunks are mapped on consecutive banks with wrap-around. All the $k$ banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes $k/2ns$.The latency of one bank access is $80ns$. If $c=2$ and $k=24$, the latency of retrieving a cache block starting at address zero from main memory is:
One of explanation I found is:
Cache block = 64 bytes.
Each bank in memory is 2 bytes and there are 24 such banks. So, in 1 iteration we can get 2*24 = 48 bytes and getting 64 bytes requires 2 iterations.
So, latency = k/2 + 80 + k/2 + 80 (since in each iteration we need to select the banks and the bank decoding time (k/2) is independent of the number of banks we are going to access)
= 12 + 80 + 12 + 80 = 184 ns
But total memory capacity here is 2*24 = 48 bytes
What I'm unable to understand is, when 1st memory access is going on, can't we decode the 2nd bank request.
So, that would make it, $12 + 80 + 80$ as in the 1st memory access of $80$, we have decoded the 2nd bank req and as soon as 1st memory access is completed, we will start the 2nd memory access which is decoded.
Are my thoughts conceptually correct? Or am I missing something?