The address bus(of cpu) is connected to a digital decoder inside the memory which sets 1 pin logic high and activates the read/write operation of the memory let's say DRAM. Is the data bus(of cpu) connected directly to the bit line of the DRAM(columns) or are there some in between steps?
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With all due reserve.
DRAM chips today are placed on DIMMs which look like
The black chips seen on the DIMM are the DRAM chips. DRAM chips inside look like
Each big gray square is called a bank. One bit of DRAM looks like
You see that between the output of the DRAM chip and the bit stored in the capacitor there is a sense amplifier. That is used to amplify the voltage of the stored energy. You need this because the energy stored in one capacitor is not strong enough to just be sent over to the bus. The sense amplifier is detailed at http://pnrsolution.org/Datacenter/Vol3/Issue2/119.pdf.
Sense amplifier is not only an amplifier but a positive feedback device that quickly pushes the readout voltage to 1 or 0. The gates of the DRAM cells are tied to the row decoder and the bit-line pairs are connected to the sense amplifier.
A detailed explanation of the hardware interface of DRAM chips is found at https://compas.cs.stonybrook.edu/~nhonarmand/courses/sp15/cse502/res/dramop.pdf. This pdf is very detailed. For the read operation it says:
To read the data from a memory cell, the cell must be selected by its row and column coordinates, the charge on the cell must be sensed, amplified, and sent to the support circuitry, and the data must be sent to the data output. In terms of timing, the following steps must occur:
The row address must be applied to the address input pins on the memory device for the prescribed amount of time before RAS goes low(tASR) and held (tRAH) after RAS goes low.
RAS must go from high to low and remain low (tRAS).
A column address must be applied to the address input pins on the memory device for the prescribed amount of time (tASC) and held (tCAH) after CAS goes low.
WE must be set high for a read operation to occur prior (tRCS) to the transition ofCAS, and remain high (tRCH) after the transition of CAS.
CAS must switch from high to low and remain low (tCAS).
OE goes low within the prescribed window of time. Cycling OE is optional; it may be tied low, if desired.
Data appears at the data output pins of the memory device. The time at which the data appears depends on when RAS (tRAC),CAS (tCAC), and OE (tOEA) went low, and when the address is supplied (tAA).
Before the read cycle can be considered complete,CAS and RAS must return to their inactive states (tCRP, tRP).
To be clear, this is how DRAM chips work with their own pins. This is not how the DIMM itself works. The DIMM is a bit different. You can look at JEDEC specifications on DDR RAM to see how DRAM work a bit better. For example, the JESD79-4 standard is about the DDR4 SDRAM (Synchronous DRAM) (http://www.softnology.biz/pdf/JESD79-4B.pdf). In this document is stated how bank groups and banks are selected. The address pins are multiplexed meaning that depending on if RAS or CAS is set then address pins will either select a column or a row. Page 5 is especially interesting because it describes the actual pins of the DDR4 DRAM chip.
To determine how actual DIMMs work, one can look at other JEDEC specifications (https://www.jedec.org/standards-documents/docs/module4_20_26_annexa). This website presents the actual document that you must be registered to download. This documents specifies the pin description of DDR4 DIMMs. The DDR4 DIMM is 288 pins (144 on each sides). The pins that are important for your question are the DQ pins. There are 64 DQ pins which is not for no reason. It is because DDR4 supports 64 bits machines. The DQ pins are probably connected to the data bus of the computer.
For actual interface between memory and Intel CPUs you can look at the External Memory Interface Handbook Volumes 1, 2 and 3 from Intel. These volumes are available on internet and are pretty lengthy. They are pretty hard to understand. The document at https://www.intel.com.br/content/dam/doc/datasheet/core-i5-600-i3-500-pentium-6000-datasheet-vol-1.pdf is a description for the core i5 processor which is pretty good. It has a pin description at the end of the document for the processor. There are 64 bidirectional SA_DQ pins and 64 SB_DQ pins. These pins are used for I/O to and from RAM.
The Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels each accessing one or two DIMMs.
Based on the above statements, there are several interfaces between the data bus and the actual bit line of the memory cell. A path will have to eventually be opened between the processor SA_DQ pins and the DQ pins of the DIMM using the data bus. The DQ pins of the DIMM are themselves connected to the output data buffers of the banks of the DRAM chips.
