How is a conditional branch instruction implemented in hardware? The instruction checks the sign bit, how does it decide to load pc with the branch address or increment pc to the next sequential address?
A modern processor will first check whether it knows the value of the condition or not. For example, if you had a C statement "if (x / y > 3) ... " then it will take quite a while until the value of the ">" condition is known. If the condition is known, then the processor knows what to do.
If the condition is not (yet) known, then things get complicated. You don't want to wait until the condition is known. The processor will therefore use branch prediction to decide whether the branch is likely to be taken or not. For example, if this branch has been performed five times before, and each time the condition was true, then the processor will guess that the condition will be true again.
However, the guess might be wrong. Therefore all the following instruction are marked as "guessed", so the processor can undo the actions of each instruction. At the same time, the processor watches the condition: In the example, once the division x/y is complete, and the comparison x/y > 3 is complete and the condition is known, the processor will know whether the guess about the condition was right or wrong. If it was wrong, then the processor undoes all the effects of instructions that were performed but shouldn't have been. If the guess was right then the processor marks all the instructions back to "not guessed". One thing that cannot be undone is storing results to memory, so while the condition was guessed, nothing has been stored to memory. All those store instructions are now started.