How is a conditional branch instruction implemented in hardware? The instruction checks the sign bit, how does it decide to load pc with the branch address or increment pc to the next sequential address?


A modern processor will first check whether it knows the value of the condition or not. For example, if you had a C statement "if (x / y > 3) ... " then it will take quite a while until the value of the ">" condition is known. If the condition is known, then the processor knows what to do.

If the condition is not (yet) known, then things get complicated. You don't want to wait until the condition is known. The processor will therefore use branch prediction to decide whether the branch is likely to be taken or not. For example, if this branch has been performed five times before, and each time the condition was true, then the processor will guess that the condition will be true again.

However, the guess might be wrong. Therefore all the following instruction are marked as "guessed", so the processor can undo the actions of each instruction. At the same time, the processor watches the condition: In the example, once the division x/y is complete, and the comparison x/y > 3 is complete and the condition is known, the processor will know whether the guess about the condition was right or wrong. If it was wrong, then the processor undoes all the effects of instructions that were performed but shouldn't have been. If the guess was right then the processor marks all the instructions back to "not guessed". One thing that cannot be undone is storing results to memory, so while the condition was guessed, nothing has been stored to memory. All those store instructions are now started.

  • $\begingroup$ Do you have any documentation to back up what you say. This doesn't seem true. $\endgroup$ – user123 Jan 10 at 19:14
  • $\begingroup$ Conditionnal branch instruction is implemented as flags registers which are checked against to determine if a condition is true or not after a cmp instruction. You basically have circuitry which is going to check the number and register you compare using the cmp assembly instruction. If the cmp is true then PC changes otherwise it is incremented to point to the next instruction. $\endgroup$ – user123 Jan 10 at 19:18
  • $\begingroup$ User123: Download intel x86 manuals, or ARM manuals, or POWER manuals. It’s simplified (branches within predicted code are more complex), and POWER loop instructions may always “know” whether they are executed or not, and execute as if you had unrolled the loop. $\endgroup$ – gnasher729 Jan 10 at 21:33
  • $\begingroup$ User123: I can’t remember ever having seen a processor where a compare instruction produced true and false. I can remember a processor where compare+branch were combined in one architectural instruction. $\endgroup$ – gnasher729 Jan 10 at 21:39
  • $\begingroup$ A cmp instruction changes some registers/flags that it will then use to jmp or not jmp when it reaches a conditional jmp. $\endgroup$ – user123 Jan 11 at 15:25

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