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How many hardware page tables (physical) and page directories are kept in the memory management unit?
If a cpu has a 32 bit virtual address, the upper 10 bits are used for the page directory, the middle 10 bits for the page table, and 12 bits for the 4K page frame. Does that mean 1 page directory containing 1042, 32 bit pointers, and 1042 page tables containing 1042, 32 bit pointers are needed?
What is the role of the page directory cr3 pointer control register in intel cpu?
The page tables are not kept in the MMU. In the MMU is a cache called the TLB which holds translated addresses. The TLB holds virtual addresses to physical addresses translations. For example, the TLB on intel core i5 has 64 entries for pages of 4KB.
Since the 10 upper bits are used as the offset in the page directory on 32 bits architecture, there are 2^10 = 1024 possible entries. The page directory has 1024 entries which hold the addresses of the page tables. Each page table has again 1024 entries holding the actual addresses of the page frames.
The CR3 register is used to locate the bottom of the page directory by the MMU. It holds a physical address (doesn't need to be translated).
