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Given an arbitrary CPU - Architecture and its instruction set... What would be the outcome of the given inverted instruction within that Architect?

For simplicity, let's use an 8-bit CPU architecture that has an 8-bit Bus design where that bus is used for both addressing and data transfer operations. A single instruction or micro instruction will act on an 8-bit string of binary digits per clock cycle. Each clock cycle may consist of 3,4,or 5 micro instructions before incrementing the instruction register for the next full instruction to be processed. These would account for the Fetch, Decode, and Execute phases of a single CPU clock cycle instruction.

The following is a mock-up only to demonstrate or illustrate my curiosity and concern while designing the layout of a given ISA(Instruction Set Architecture)...

Here we have the range of possible instructions from [0000 0000, 1111 1111] which are all of the possible permutations that this arbitrary CPU-Architecture's Machine Language can support. We could use Ben Eater's 8-bit Bread Board CPU and its ISA as an example... You can find that here along with other useful videos from his YouTube channel: Comparing C to Machine Language, and Programming 8-Bit Computer. With his given implementation, the first 4 bits are used to define the instruction and the second 4 bits are used for data {either memory address or immediate value}...

Now to my question: Given a specific instruction word and its accompanying data field, what would be the resulting outcome if we invert all of the instruction bits?

First, I know that this would be independent on each Architecture's ISA design implementation... Second, I'm just curious to what the ramifications would be when designing your own specifications in that, would it be possible to carefully design and layout your bit fields per instruction in a manner that you could have a special invert operation, that would automatically invert a given instruction where that inversion would produce the opposite or inverse effect of the given incoming instruction? Now, the inversion won't necessarily happen to the entire instruction string that includes all 8-bits, but only to the bit-fields that pertain to the instruction type while preserving the data field... For example:

  • If we have an Add instruction, the invert op would turn this to a Sub...
  • If we have an And instruction, the invert op would turn this to an Or instruction...
  • If we have either a Bit Shift Logical Left or Bit Shift Arithmetic Left, the invert op would respectively turn these into Bit Shift Logical/Arithmetic Right operations...
  • And so on...

Would such a design be possible to have perfect symmetry within it's ISA?

-Note- I don't know if this is the correct StackExchange site for this question... if it is not please don't down vote it due to being irrelevant and be kind enough to point me in the right direction letting me know where the appropriate site for this question would be.

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If you are decoding instructions using logic based on individual bits in the opcode, this "inversion' scheme is probably counter productive. If the opcodes are decoded using a simple table lookup of the "value" of the opcode, then the actual pattern of the opcode is just arbitrary and the inversion scheme is just as valid as one based on the alphabetic order of the mnemonics.

For stack based machine, variable length opcodes could be more valuable, shorter opcodes for push, pop, and any immediate value instructions to give more space for address or data bits.

Self-modifying code has been out of fashion for decades, so being able to flip the meaning by inverting the bits would seem to have no utility.

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  • $\begingroup$ I've hot patched OS code by halting the machine (IBM1130) and using the switches on the panel to change an instruction by entering the binary of the new instruction and storing at the selected address. then restarting What this has to do binary inverted opcode is beyond me. $\endgroup$ – jfwfmt Feb 22 at 18:57
  • $\begingroup$ I appreciate the insight. This question was inspired by watching videos on how the Navigational Computer used by the Apollo Missions was designed. In today's standards, it would be considered completely unconventional. It was made with NOR gates instead of NAND gates, it used 1's Compliment Arithmetic instead of two. It had no floating point arithmetic in hardware, yet the design and its capabilities were much farther ahead of their time. It was about the size of a small briefcase, weighed only a few Kg and consumed only about 55 W of power. It's operating system was even more impressive. $\endgroup$ – Francis Cugler Feb 22 at 23:31

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