# About the connection of pipelined execution and latency

Let's consider we want to calculate a[i]=a[i]*c for a vector the size of N=12 on some random processor.

We do assume that c is some given constant already present in the register. We do not consider any superscalarity or vectorization. We also know the latencies for the following instructions:

• Load operand to register (4 cycles)
• Multiply a(i) with c (2 cycles); (a[i],c in registers)
• Write back result from register to mem./cache (2 cycles)
• Increase loop counter as long as i less or equal N(0 cycles)

The result my class gives me for the pipelined execution of this is the following, where each line represents one CPU cycle:

Why is this correct? Or is this even correct?
If we consider the first load (load a[1]) shouldn't it block my only load unit on the processor for 4 cycles? How can I even load a[2]in cycle 2then?

Or is latency only the time to that is needed to send information that something is e.g. loaded, and the actual load unit is only busy for one cycle for each load operation?