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L1: LD F1,0(R2)
L2: LD F2,8(R2)
L3: FADD F3,F1,F2
L4: SD F3,8(R2)

If the instruction fetch for L1 starts at clock cycle 1, in which cycle the instruction L4 access memory to store the data?

I am getting the answer as 8 but the correct answer is 11. Could someone help here?

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