Given that the MMU does all the memory translations and etcetera, how does it maps a system consisted of multiple RAM chips?

Are their spaces concatenated (e.g Chip 1 + Chip 2)? If so, how does that works given ASLR?

  • $\begingroup$ (contemporarily, the components that can be handled individually are memory modules, not single chips. I don't know of current modules concatenating address spaces of chips, but there are those presenting multiple banks.) $\endgroup$ – greybeard Mar 26 at 7:35
  • $\begingroup$ I don't see the connection between Address Space Layout Randomization and mapping between addresses&modules/chips. $\endgroup$ – greybeard Mar 26 at 7:37
  • $\begingroup$ @greybeard Yes, I used the terms wrongfully, what I was trying to say was memory modules indeed. And great! I thought ASLR was laid out by the hardware, thanks for the info. $\endgroup$ – Segmentation Fault Mar 26 at 11:21

ASLR has nothing to do with this. ASLR is a software technique to secure the applications where all executables are relocatable in that they keep information in the executable to relocate it to any address.

I would guess that the MMU doesn't see if there are several RAM DIMMs. It is the motherboard's job to make sure that if the memory controller of the CPU sets certain lines of the address bus, they are directed towards the right DIMM for decoding.

In hardware it could look like switches (transistors) activated by higher order bits of the address bus that will redirect all address lines to another DIMM. For example, if you have 2 DIMMs of 8GB each then the first DIMM needs 33 address lines for decoding because 2^33 bytes = 8GB. The second DIMM brings the computer to 16GB so, if you set any line of the address bus above 33, then the motherboard knows it needs to use the second DIMM.

  • $\begingroup$ Nice! So they are indeed just "concatenated". And makes sense that the MOBO does this translation given we have DMA as well. Thanks! $\endgroup$ – Segmentation Fault Mar 26 at 11:26

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