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While reading about interrupt mechanism, I understood that there is an IRQ signal line on the bus by which an I/O interface raise an interrupt request.

There is an INTA signal line using which the processor indicates acceptance of to the interrupt request.The processor interrupts the program currently under execution, saves the current PC & PS in the stack and transfers control to the ISR meant for the I/O device concerned.

After completion of execution of the ISR the processor restores the saves PC & PS so as to resume execution of the interrupted program.

But can anyone help me to understand in depth about the mechanism for interrupt enabling and disabling.

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The process that you've described happens only if interrupts are enabled. The IRQ request (via INTR line) asks the CPU to handle the interrupt. If the CPU accepts, it will issue an INTA as you describe.

The CPU doesn't always accept interrupts. For instance, if the CPU is "in the middle of something", then it might delay handling the interrupt (for instance, until the instruction which is currently being executed, finishes). Additionally, the CPU has an internal flag that indicates whether or not is should accept interrupts. In the x86 family, this is the IF (interrupt flag), and you can control it by the commands STI (set interrupt flag == enable accepting interrupts) and CLI (clear interrupt flag == disable accepting interrupts). In other CPUs the naming might be different or there might be a more sophisticated mechanism setting/clearing interrupts of specific type/priority.

If the IF is cleared and interrupts are disabled, the CPU just "ignores" the input INTR line. This is known as masking interrupts. The CPU just continues as if the INTR line is low... Once you set the IF, then the CPU will stop ignoring the interrupt and will handle it according to the standard procedure (save flags and return address, and jumps to the ISR, issuing INTA, etc.)

Just to make it clear, enabling/disabling interrupt does not change the way the external I/O creates the interrupt. It just changes the way the CPU behaves in case of an external interrupt: if enabled, the interrupt is processes. If disabled/masked, interrupts are ignored.

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For x86 it is a bit more complex today. Especially with the advent of PCI. Most of that IRQ stuff you're talking about is emulated today and obsolete. Most devices I can think of, that people are using the most today, are devices connected to PCI devices. For example USB is connected to the xHCI PCI device, SATA drives are connected to an AHCI PCI device, network cards are PCI devices, graphics cards (even Intel HD Graphics integrated in your CPU) are PCI devices. Everything is a PCI device.

Mostly, this IRQ method of having a line per device is over. That was how it worked with the old 8259 PIC but today it is just being emulated. Especially, with the mandatory MSI/MSI-X capability of PCI-Express devices (if they follow the spec).

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