The process that you've described happens only if interrupts are enabled. The IRQ request (via INTR line) asks the CPU to handle the interrupt. If the CPU accepts, it will issue an INTA as you describe.
The CPU doesn't always accept interrupts. For instance, if the CPU is "in the middle of something", then it might delay handling the interrupt (for instance, until the instruction which is currently being executed, finishes). Additionally, the CPU has an internal flag that indicates whether or not is should accept interrupts. In the x86 family, this is the IF (interrupt flag), and you can control it by the commands STI (set interrupt flag == enable accepting interrupts) and CLI (clear interrupt flag == disable accepting interrupts). In other CPUs the naming might be different or there might be a more sophisticated mechanism setting/clearing interrupts of specific type/priority.
If the IF is cleared and interrupts are disabled, the CPU just "ignores" the input INTR line. This is known as masking interrupts. The CPU just continues as if the INTR line is low... Once you set the IF, then the CPU will stop ignoring the interrupt and will handle it according to the standard procedure (save flags and return address, and jumps to the ISR, issuing INTA, etc.)
Just to make it clear, enabling/disabling interrupt does not change the way the external I/O creates the interrupt. It just changes the way the CPU behaves in case of an external interrupt: if enabled, the interrupt is processes. If disabled/masked, interrupts are ignored.