It is false to assume that a write to a cache-line will cause a flush to main memory. Caches on modern CPUs are always coherent. Modern caches are also write behind caches meaning that in theory they never need to write to main memory. The primary reasons for a cache-line to end up at main memory are:
- lack of space in the cache.
- limitation in the cache coherence algorithm. E.g. with MESI if a different CPU wants to read a dirty cache-line, the cache-line needs to be written to main memory to prevent the change being lost. MOESI solves this problem.
- I/O DMA.
Cache coherence provides 'coherence':
- a total order over all loads and stores on a single address.
- a read needs to see the most recent write before it this order.
In very simple terms: cache coherence provides sequential consistency per address.
An example test for #1:
Can it be that r1=1, r2=2, r3=2, r4=1 (so CPU3 saw the changes in different order than CPU4). No. this is not allowed.
An example test for #2:
Can it be that r1=1 and r2=0? So are you allowed to see a 'stale' value once you read a newer value? No, this can't happen because once you see 1, you can't go back in time and see the value before it.
Coherence is the key to understand any memory model. If you don't understand coherence, everything you build on top remains fragile. In almost all modern processors (GPU is the only exception I know of) caches are always coherent.
For an excellent read on the topic, see A primer on memory consistency and cache coherence second edition.. The book can be downloaded for free which is pretty amazing seen the quality of the book.