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For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary?

  1. L1 must be a write-through cache.
  2. L2 must be a write-through cache.
  3. The associativity of L2 must be greater than that of L1.
  4. The L2 cache must be at least as large as the L1 cache.

This was a multiple-choice question with the following possible answers:

  • (A) 4 only
  • (B) 1 and 4 only
  • (C) 1, 2 and 4 only
  • (D) 1, 2, 3 and 4

I think L2 cache must be at least as large as the L1 cache but I am confused what the need for writeback is for this cache.

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    $\begingroup$ Please include your own effort as well. $\endgroup$ – Juho Sep 6 '13 at 13:36
  • $\begingroup$ I think L2 cache must be atleast as large as the L1 cache but i am confused about what is the need of writeback for this cache $\endgroup$ – user10012 Sep 6 '13 at 13:43
  • $\begingroup$ This is a dump of a homework/exercise problem, not a question. If you have a specific question regarding the wording of the problem or about concrete steps in your own attempts at solving the problem, feel free to edit accordingly and we can reopen the question. See also here for our homework policy, and here for a relevant discussion. You may also want to check out our reference questions; your problem may be covered there. $\endgroup$ – Raphael Jan 24 '14 at 17:13
  • $\begingroup$ @Raphael, I don't know why you have closed this question (and tagged unclear). This is a question asked in GATE 2008 (an exam organized by Indian Institute of Technologies). SE homework policies does not give you the right to close topics, as you have done here. Essentially you have blocked some potential answers and ideas to be revealed here. You can see the discussion list here and may infer how you have blocked the flow of other answers and concepts in a bigger community, like SE. $\endgroup$ – pratyay Jul 4 '18 at 13:03
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Correct Answer: 1) and 4) only . For inclusion property to hold, every changes in L1 should be made in L2 also. therefore , L1 should be write-through. It is not necessary fr L2 to be write -back. And 4) is mandatory for the same reason i.e L2 would need to hold the contents as same as L1 and as much as ,or may be greater than L1.

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    $\begingroup$ I assume you meant "write-through" not "write-back". It might also be noted that L2 caches can be considered inclusive even if the data in L2 is stale, i.e., (consistent-)data-inclusive is a subset of tag-inclusive. Even with no indication of inconsistency/L1 ownership, a tag-inclusive L2 cache would filter coherence probes (an L2 miss is guaranteed to be an L1 miss) and adding a little extra state to L2 tags to track the state of L1 (to further avoid L1 probing) is much less involved than supporting write-through in L1. $\endgroup$ – Paul A. Clayton Dec 9 '13 at 16:29
  • $\begingroup$ Yes, I meant write through. Sorry about that... And thanku Paul for the information. :-) $\endgroup$ – Rashmi Badole Dec 11 '13 at 9:22
  • $\begingroup$ In real CPUs, Intel Nehalem and later use tag-inclusive L3 to keep track of what the private per-core L1I/L1d / L2 caches might hold, instead of broadcasting invalidate / RFO requests (i.e. snoop requests) from each core to all cores. $\endgroup$ – Peter Cordes Apr 12 '18 at 4:02

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