In order to use large size page table hierarchical paging is done . In case of two level page table scheme . for : logical address space - 32bit - $2^32$ page size - 4kb i.e $2^12$
It is mentioned that page number is divided evenly :
i.e page number p1 - 10 bits page number p2 - 10 bits page offset d - 12bits.
I got this...... but my question is different. I didn't get the concept behind it.
What I thought for that I will take 1 example.
Take the address
0x00FF1234. The binary representation of this address is
00000000111111110001001000110100. By splitting this up, we get
0000000011 1111110001 001000110100, or
0x3 0x3F1 0x234.
0000000011 this number is pointing to 4th entry in the 1st level table. Means there are
1111111111 unique numbers ( entries ) in the 1st level table. These gives the address of the 2nd level table.
In this we are referring
0000000011 entry. Now does this entry contain some address which points to the base of the 2nd level table ? Now we are being pointed to 1111110001 address means
1111110001 address ( I am thinking ) if yes then why only that address ? why not other address ?
Means here I want to ask what exactly happens behind this jumping. And how ? I read somewhere here about
CR3 register and all that but didn't get anything. I don't want that much deep. I just want to solve basic example of paging , TLB , virtual memory for GATE exam.
And what is this page size ( I always consider it as d as offset and solving problem )
For example : Page size is 1024 byte ... means d = 10 bytes. Does it mean , it ranges between 000....( 10 times) to 111....( 10 times) ? Not getting this concept properly.