FSM+Datapath, in this context, is a design technique of logic design. Any real-world sequential circuit can be modeled as an FSM, but in practice only sequential control logic is modeled as an FSM. For example, a D Flip-Flop can be modeled as an FSM, i.e. in terms of explicit states and their transitions, or it can be modeled in terms of logic gates, or a behavioural description with implicit states. Whichever method you use for modeling a D Flip-Flop, the D Flip-flop remains an FSM, but only when the design is expressed in terms of explicit states and their transitions, do we say the flip-flop has been designed using the FSM design technique. Similarly, only when a logic design is modeled using the explicit flow of data, do we term it as datapath design technique.
To answer the question of why FSM+Datapth became the dominant technique, we should look into some of the alternatives to FSM+Datapath that exist, and why these alternatives failed.
Synchronous logic vs. Asynchronous logic
FSM + Datapath is a term often used for synchronous logic design of sequential logic. While asynchronous FSMs do exist, the most common ones are synchronous. Asynchronous logic does not use a clock for synchronization, while synchronous logic uses a global clock for synchronization of operations. In synchronous logic, the FSM changes its state on the active edge of the clock. So the operation is predictable and it is regular. The change of state happens at regular intervals of time, since the clock frequency is constant (varying clock frequency dynamically is also possible, but let's keep things simple for our discussion). In asynchronous FSM, change of state is not synchronized with a clock. Synchronous logic is much easier to design. The logic is less complex, so it is easy to get a correct design using synchronous logic. This is the reason all the processors we use in daily life are synchronous.
Top-down methodology vs. bottom-up methodology
The bottom-up methodology focuses on designing the circuit from the bottom-up, i.e. from transistors to gates to the final circuit. The top-down methodology focuses on designing the circuit from higher-level abstractions, such as behavioral descriptions and flow-diagrams. While the bottom-up methodology works well for smaller design blocks, it does not scale up for large designs such as processors. This is the reason a top-down methodology is used for processor design. In practice, smaller functional blocks are designed bottom-up, and the entire system is designed top-down, and the 2 meet in the middle, i.e. the system is broken down into smaller blocks, which are designed from the bottom up.
A top-down methodology has 3 advantages over a bottom-up methodology:
- Promotes regularity: This refers to designing a complex unit using simpler units repeatedly. For example: Designing a 4 bit adder using 4 1-bit adders.
- Promotes design reuse: The top-level design can contain many units, which can be broken down into even more units. Different design units can have a common design for the lower-level design units. For example, both a 4-bit adder and a 4-bit multiplier can have a common design of a 1-bit adder. Multipliers can be built from shifters and adders.
- Ease of design: The designer does not get lost in a sea of gates when designing a complex unit. The processor architect (system-level processor designer) can split the design work among multiple teams, so design work can be done in parallel.
All these factors result in far lesser design time for a top-down methodology than a bottom-up methodology. As time-to-market is crucial in the semiconductor industry, this resulted in top-down methodology becoming the methodology of choice.
Motivation for Finite State Machines
For controlling sequences of operation, it is natural to think of it in terms of how the machine should behave, rather than how the machine should be implemented using logic elements such as Flip-Flops and combinational logic. This led to the evolution of FSM design technique. In this technique, the FSM is implemented using gates and flip-flops, from the behavioral description of the FSM, in a top-down design methodology. The behavioural description of the FSM contains explicit states and state transitions in the FSM Design technique.
Motivation for Datapath
For operations in which I need to move my data around, for example from register to memory or register to register, it is natural to think about how the data should flow. By thinking this over, I can then draw an abstract diagram of the datapath. This led to the evolution of the datapath design technique. In the datapath design technique, the datapath is implemented using combinational logic and registers, from the datapath diagram, in a top-down design methodology. The behavioural description of the datapath contains explicit flow of data in the Datapath Design technique.
Putting it all together: Motivation of FSM+Datapath for processor design
So while the FSM design technique excelled at designing control logic of sequences, the datapath design technique excelled at designing logic to support the flow of data. Coming to the processor, it is natural to split the design of a processor into 2 parts:
- The sequence of operations: Fetch data from memory, decode the instruction and then execute it, finally write it back. We use control signals to signal the completion of one operation and flow control (such as branching). This control of sequences can be designed naturally using the FSM design technique.
- The flow of data: How data should flow from register to memory or register to ALU and so on. This can be designed naturally using the datapath design technique.
Availability of EDA tools:
The availability of Electronic Design Automation (EDA) tools played a crucial role in enabling a top-down design methodology and the synchronous design philosophy, since EDA tools had great support for logic synthesis (automatically generating logic gates from a behavioral description) for synchronous designs, and also had great support for logic synthesis from an abstract, behavioural textual description written in a special computer language called a Hardware Description Language.
Summary and conclusion:
Synchronous logic became the dominant design technique simply because it was easier to design working machines. FSM design technique by itself is limited in usefulness, since it would be difficult to create an FSM for the entire processor, because this would result in a very large and complex FSM that is difficult to debug or read. Sequential control of the processor can be designed naturally using the FSM Design technique, so only the sequential control of the processor is designed using the FSM design technique. The rest of the processor is designed using the datapath design technique, since the dataflow aspect of the processor is easy to model as a datapath. The availability of EDA tools further motivated the design of processors using abstract, behavioural descriptions such as FSMs and datapaths.
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