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Assuming you know the meaning of pipelining in Computer architecture & organization. When is the next PC address or jump address available or known to the processor?

In this lecture, https://youtu.be/TMpjvAvQCWA?t=2346

Jump and branch addresses are computed during EXE or execution stage and are good to go ahead but I can't quite seem to understand why?

This concept is quite not available on websites out there and therefore, my apologies if wrong terms used here.

Thanks in advance.

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  • $\begingroup$ Can you please be more specific? Is your question "Why is the next instruction to execute (i.e. the next PC) not definitely known before the execution stage?"? $\endgroup$
    – idmean
    Jul 17 '21 at 15:15
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You can start with a simplified mental model: There is a program counter. The processor reads the instruction pointed to by the program counter, executes it, calculates the start of the next instruction to be executed, stores it into the program counter, and we start all over.

There are cases when the "next instruction" isn't stored after the previous instruction; when we have a branch instruction, or a conditional branch instruction (where we have two possible locations for the next instruction), and there are subroutine calls, where the processor needs to store the address of this or the next instruction in order to return. Just to make it more complicated.

In a simple pipelined processor, we'd want to read the next instruction as quickly as possible after reading the previous instruction. So the chip designers will do the utmost to make sure that the address of the next instruction is known in the next cycle, if at all possible. That involves determining the length of the current instruction as quickly as possible, checking that it is a branch instruction as quick as possible, and in case of a conditional branch either determine or guess the location of the next instruction as quick as possible. So in one cycle you would try to read the instruction, determine its length, and determine that it is a branch, so the program counter is known in the next cycle if at all possible.

In today's multi-issue processors, the processor will decode several consecutive instructions in the same cycle. Some instructions are complicated and their length may be hard to determine, and only one such instruction can be handled in a cycle. But other times you might have four very simple instructions in a row, and the processor can start executing all four of them, calculating only the program counter after executing the fourth instruction. The address of the 2nd, 3rd and 4th instruction might never make it into the program counter.

And then there are processors which translate instructions into RISC instructions. Such a processor may rarely know the program counter, but be able to determine the program counter if needed.

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Today's processors work very differently. I.e., current Intel ones translate the CISC instrunction into a sequence of internal RISC instructions, which are scheduled on the fly to execute on the multiple internal functional units using the internal register files that shadow the programmer visible ones.

In any case, the address(es) for the next PC are available as soon as they are read or computed. If it is an absolute jump, it is part of the instruction, indirect jumps of any sort require further analysis/processing. Some processors even speculatively execute one or both branches of a conditional jump before deciding which way to go, discarding the one that doesn't pan out.

Most textbooks discuss technology as it was some decades ago, and then simplify/organize the material (reality is much messier than theory). Remember that literally hundreds, if not thousands, of engineer-years went into the design of current chips. You just can't compress all that into a few weeks of class time.

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