Edit: Here's maybe a clearer presentation of my question. In a Boolean formula, all the gates have fan-out 1, and the graph representing the formula is a tree. In a Boolean circuit, the gates can have multiple outputs. What can be said about formula size as compared to circuit size?
I am learning some basics about classical circuit complexity, and have a confusion centering around the role of fan-out.
In various references (e.g. the textbook by Vollmer), circuit size is defined with respect to a basis where each gate has fan-out 1, like say AND, OR and NOT. A natural, simple operation seems to me to be fan-out, where I just copy a bit so it can be used twice in the circuit.
I am wondering how allowing fan-out changes the size of a minimal circuit computing a Boolean function.
A naive observation is that if I have a circuit of depth d that uses fan-out (say with two outputs), I could replace it with a circuit without fan-out while increasing the circuit size by at most $2^d$ (make a copy of the circuit below each fan-out, to compute that bit twice). Unless $d$ is $O(\log n)$ for $n$ the input size, this changes a polynomial size circuit to a super-polynomial one, so at least using this observation alone fan-out seems to have a notable effect on circuit size.
Is there a better way to remove fan-out gates than the above? Or is there a motivation for focusing on notions of circuit size / complexity that exclude fan-out?