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I am studying direct mapping in cache. I understood the concepts like dividing into blocks and lines , tag directory etc. When solving numerical problems of finding main memory size or tag directory size I have no problem. What I understood is that, in cache we have a tag associated with each cache line ( neglecting valid/invalid and other bits ) and size of each line is equal to block size.

So size of cache should be - Tag Directory Size + Size of each line * No of lines .

But when the guy( here ) is not adding tag directory size to cache size. Why is it so? Or I misunderstood the concept?

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The term "cache size" generally refers to its data capacity, not to the sum of the data capacity plus all the other stuff as well. Similarly, the "state" bits, masks, LRU indicators, ECC bits, and so on, wouldn't be included in the "cache size", because they don't add capacity. It's similar to how a 1L bottle really takes up more physical space than 1L, the 1L refers to how much fluid the bottle can contain, not to the "total size". Of course the other things are stored somewhere too, and you could add up all the sizes, but that's not what is typically meant by "cache size".

While the tags and data could be put into one big SRAM array (and abstract diagrams usually show it that way), often they're stored separately.

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  • $\begingroup$ thanks now I understood that it actually means data holding "capacity". So, tags are stored in cache? Or is there anything( which is used in mapping ) that is stored somewhere else. $\endgroup$ Oct 6, 2021 at 6:26
  • $\begingroup$ @Brijeshjoshi as I mentioned already, the tags are often stored separately. There are some examples of that here with P4's L2 tags $\endgroup$
    – harold
    Oct 6, 2021 at 6:41

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