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Are they exactly 32bits for a 32-bit system ?

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It depends.

To see what I mean, I'm going to take the Intel Pentium Pro as an example. This was top of the line in consumer hardware in 1995 (which, you will recall, was 25 years ago).

It had 32-bit integer registers, giving 32-bit integer arithmetic and a 32-bit virtual address space.

However, it also supported a 36-bit physical address space.

The external connections to the chip (I'm going from the data sheet, table 29 here) had address lines A3 through A35 and data lines D0 to D63. So that's 33 bits of external address bus, and 64 bits of external data bus. You can count the control lines for yourself if you are curious.

Remember, modern CPU cores generally don't write directly to and from memory, but rather write directly to and from cache. On the Pentium Pro, the on-chip cache line size was 32 bytes, so this is how the CPU could handle a 64-bit external data bus despite not being a 32-bit CPU: transfers from cache to RAM (and vice versa) used a burst of four 64-bit-wide transfers.

(Disclaimer: I don't know how uncached memory accesses, such as memory-mapped I/O, worked on the level of physical signals. It's probably in the data sheet, but this is beside the point I want to make here.)

While there is no strict definition of what constitutes "a 32-bit CPU", but we can safely assume for the sake of argument that we're talking about 32-bit integer registers, 32-bit integer arithmetic, and 32-bit virtual address space. So 32-bits is an abstraction. It is what a programmer sees.

A hardware designer, working at the level of pins and signals, may see something very different.

To a modern CPU, RAM is more like a peripheral than something directly attached to a CPU core. The core interacts with cache, and caches communicate with RAM (and other caches, in a multiprocessing environment) as if they were a device. Modern thinking on device interfaces is that transfers should be in "bursts" if possible, because it increases the amount of data that you can transfer for a given setup.

It gets even stranger than that. If you think of RAM as a device, then at boot time, that device may not have been initialised yet. Many modern CPUs can configure their cache controllers not to talk to RAM, so it effectively runs using cache only until enough of the peripheral hardware is initialised.

By the way, we haven't talked at all about the width of internal busses. In a superscalar CPU, that's a huge topic by itself, because the common data bus may, in reality, be multiple independent busses so that multiple instructions can be scheduled and retired in the same clock cycle.

We have also ignored floating point; most 32-bit CPUs support 64-bit floating point arithmetic, and hence any registers and internal busses must be able to handle that somehow. The Pentium Pro had floating point registers were 80 bits in width, and the P6 microarchitecture (of which the Pentium Pro was the first CPU) eventually supported 128-bit SIMD registers and streaming vector arithmetic.

So, back to the question you asked:

If a 32-bit computer system is being used, what are the size of the data/address/control bus width? Are they exactly 32bits for a 32-bit system ?

It depends exactly what you mean by that question, but for the last 20 years at least, probably not.

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    $\begingroup$ +1 for such a detailed answer. Bringing in the data sheet is just WOW but could be intimidating at first, but the best and absolute source of truth! $\endgroup$ Oct 18, 2021 at 5:25
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A k-bit system has registers of size k bits i.e. each register is k bits in length (size), and, these are the primary units of data transfer. These are also called word and word-size. Data transfer to and from CPU happens in chunks of words, so, for a 32-bit system, 32-bit word is what drives data.

Now, chunks of words is the key here. There are many kinds of transfer happening - DATA, INSTRUCTIONs etc. So all these happen in multiples of word.

You can find some detail here

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