I'm reading section 7.3 (SINGLE CYCLE PROCESSOR) of Digital Design and Computer Architecture, Second Edition by David Money Harris.

At the end of the section the autor shows this MIPS processor and says that "Each instruction in the single-cycle processor takes one clock cycle".

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The autor also says that "Result must setup at the register file before the next rising clock edge, so that it can be properly written". If I'm correct, he is saying that the processor has the whole cycle time to execute that instruction, but Result should be present at the rising edge of the clock of that same cycle because the PC, Register File and Data Memory are changed only during the clock edge. Thus, the processor has only the rising time, not the cycle time, to execute the instruction.

I don't understand how he can say that an instruction can be executed in one cycle time if the elements are chained like that and even the Register File has to wait for its own result to be processed and arrive at WD3 in the same cycle.


1 Answer 1


The register file in this design is multi-ported, and the read ports work like combinational circuits. The only thing between the read input and the output port is propagation delay. The clock signal is only needed to write a value.

The same is true for data memory, which is assumed to be a combinational circuit for the purpose of issuing a read.

If the value of a register is modified, and then the same register is read on the next instruction, then there may be a propagation delay before the newly-loaded value is valid at the read port, but that's a limitation on the clock speed, not on the correctness of the data path. As long as the input to a latch is correct at the time the latch is loaded, the CPU will work correctly.

  • $\begingroup$ I don't understand. The signals follow the data path (the dashed blue line). What I think is that they must complete their path and arrive at WD3 before the rising edge finishes, because the clocked elements only accept signal on the rising edge. Is this correct? $\endgroup$
    – EmTor
    Commented Apr 13, 2022 at 3:38
  • 1
    $\begingroup$ The clocked elements only accept their signal on the rising edge, that is correct. The read ports on the data memory and the register file are NOT clocked elements. Only the write ports are. $\endgroup$
    – Pseudonym
    Commented Apr 13, 2022 at 7:46

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