I'm reading section 7.3 (SINGLE CYCLE PROCESSOR) of Digital Design and Computer Architecture, Second Edition by David Money Harris.
At the end of the section the autor shows this MIPS processor and says that "Each instruction in the single-cycle processor takes one clock cycle".
The autor also says that "Result must setup at the register file before the next rising clock edge, so that it can be properly written". If I'm correct, he is saying that the processor has the whole cycle time to execute that instruction, but Result should be present at the rising edge of the clock of that same cycle because the PC, Register File and Data Memory are changed only during the clock edge. Thus, the processor has only the rising time, not the cycle time, to execute the instruction.
I don't understand how he can say that an instruction can be executed in one cycle time if the elements are chained like that and even the Register File has to wait for its own result to be processed and arrive at WD3 in the same cycle.