Pipelined processors suffer from stalls due to different kind of hazards and one way of dealing with it is to implement forwarding of different types. For example ALU-ALU forwarding or full forwarding (MEM stage -> EX stage). A result of implementing forwarding in a pipelined processor is that we get an increased throughput as we have reduced the amount of stalls. According to my teacher forwarding can potentially impair performance too but he didn't go into much detail at all and as such I am left curious about what exactly he meant. I have tried to find information about it but to no avail. One thought I have is that it might impair performance in the sense that it makes the processor slower as extra logic is added to support the forwarding step. Can forwarding in pipelined processors impair performance in any way, if so how?
Modern cpus have deep pipelines with 20 stages or more. Attempting full forwarding would require far too many bypasses to be practical. For example, if the depth is 20 the first stage would be connected to 19 bypasses, the second 18 bypasses, the third 17 bypasses, and so on. This would consume way too much silicon for wires, muxes, and control signals, so bypasses are only added for the commonly used cases. And even with all these bypasses, the cpu would still stall waiting for memory and in other situations.
Take an out-of-order processor. At any cycle, there may be multiple instructions ready for execution. The choice which to execute next can affect the total execution time in unpredictable (for the processor) ways.
Register forwarding can lead to a different instruction being executed next, with a different total execution time, which may be longer. But you save one cycle, and you will save more cycles by more forwarding, lo losing out is unlikely. Not impossible but unlikely.