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Gandalf61 mentions here that there are opcodes that "load the next word into Register A", treat the bits at the next address defined by program counter as data and loads this data. I am interested in examples of computers and CPUs that have such as opcode.

Context: Learning basic computer architecture, and interested in how to load constants into registers. In nandgame.com and "nand to Tetris" course (that uses "hack computer" and "hack assembly"), there is "a-instruction", specified by 15th bit set to 0, that treats the instruction as 15 bits of data. With "load immediate" instruction (or similar name) in a few real-world CPUs I read about, a few bits will be treated as data and loaded into register. I am interested overall in how a constant defined in assembly or in a program gets into the CPU. Have not seen any that worked like Gandalf61 mentioned, therefore asking.

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  • $\begingroup$ (I seem to remember few architectures that don't feature a word size load immediate, whether as a separate op code or via one addressing mode of a load instruction. MIPS for one had to assemble word size literals, use of LUI (Load Upper Immediate) was suggested.) $\endgroup$
    – greybeard
    Jul 17, 2022 at 6:24
  • $\begingroup$ Thanks yes I came across the LUI approach too. I mostly want to know how much of what I learnt from nandgame is "real" and how much is simplified fiction, and what Gandalf61 mentioned seems reasonable, but have not seen in anywhere (maybe he was "simplifying" and that type of instruction, "load next word into register", has not been used. ) $\endgroup$
    – user52174
    Jul 17, 2022 at 12:11

2 Answers 2

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Many/most architectures include this kind of instruction. It might be known as "load immediate" or "move" with an immediate/literal/constant value. See, e.g., https://en.wikipedia.org/wiki/Addressing_mode#Immediate/literal, https://en.wikipedia.org/wiki/Instruction_set_architecture#Data_handling_and_memory_operations, or look into the instruction sets of any of your favorite computer architectures.

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    $\begingroup$ Thanks, I was specifically wondering about where an opcode specifies that the next word (not part of the current word) should be loaded into some register. The "load immediate" seems to specify that part of the current instruction should be loaded/interpreted as data, not the following instruction. $\endgroup$
    – user52174
    Jul 17, 2022 at 8:04
  • $\begingroup$ @user52174, you might have to review some instruction architectures to see what you can find, then. In some architectures, such as x86, there is no notion of "current word" or "next word". $\endgroup$
    – D.W.
    Jul 17, 2022 at 16:34
  • $\begingroup$ ok that sounds weird. do you have any reference to it or link to any good place to read about it? $\endgroup$
    – user52174
    Jul 18, 2022 at 1:51
  • $\begingroup$ @user52174 you can look up the x86 mov instruction - it has lots of versions - the ones that load 32 bits are 32 bits longer than the ones that don't. You could think of it as a "next byte" and the CPU reads 4 extra bytes after the instruction. x86 instructions have variable length (even the instruction part) and we think of the value as part of the instruction. The "next word" thing is more applicable to architectures where every instruction is the same size. $\endgroup$
    – user253751
    Jul 18, 2022 at 15:10
  • $\begingroup$ @user253751 Thanks. Have looked at the mov instruction during my study of how data in program would be loaded into register. To use mov on x86 for that, is it something like mov some_register, constant_value, for example mov EAX, 4294967295 or mov EDX, 4294967295? I assume you do not mean something like "mov EAX, [EIP]" (I assume EIP is program counter), it would be closer to how I interpreted Gandalf61's comment (and I also assume such an instruction would not increment program counter and therefore not work very well. ) $\endgroup$
    – user52174
    Jul 18, 2022 at 15:49
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Expanding on the comments about x86:

One of x86's "load immediate" instructions is MOV eax, 0x11223344 encoded as B8 44 33 22 11 (x86 is little-endian).

There are two ways you could view this instruction.

Officially, it's a 5-byte-long instruction MOV eax, 0x11223344 which stores the value 0x11223344 into eax.

But you could also view this as a 1-byte instruction MOV eax, next 4 bytes from EIP (encoded as B8) followed by the 4-byte value 0x11223344.

These are two different ways to think about the exact same machine code bytes which make the processor do the exact same thing.

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  • $\begingroup$ Thanks. But, I still do not think "MOV eax, next 4 bytes from EDX" seems like it would increment the program counter an extra step (and skip over the next instruction that might be 0x11223344. ) So I still do not see that "MOV eax, next 4 bytes from EIP" would (and then jump directly to the instruction after "0x11223344". ) And if it does not, then it can't be exact same machine code bytes. I might be missing something, this is my thoughts at the moment. $\endgroup$
    – user52174
    Jul 18, 2022 at 18:18
  • $\begingroup$ I've tested it as far as I could in x86 emulators now, and it does not seem possible to do MOV eax, [EIP] with the number after that as its own "instruction" and get exact same machine code as MOV eax, number. It only increments the program counter by one, so it would not make sense. And getting the value for the instruction pointer seems a bit tricky as well, to start with. $\endgroup$
    – user52174
    Jul 18, 2022 at 22:22
  • $\begingroup$ @user52174 There is no "MOV eax, next 4 bytes from EDX" instruction. If there was, it would increment EDX by 4 bytes, not EIP. Some architectures do have this type of instruction. $\endgroup$
    – user253751
    Jul 18, 2022 at 22:24
  • $\begingroup$ You are the one who mentioned "hypothetical" incrementing EIP, "there is literally no difference between "mov EAX, 0x11223344" and (hypothetically) "mov EAX, [EIP++]" followed by 0x11223344. They make the exact same bytes of machine code and do exactly the same thing". Now you deleted that, but as I said, it does not at all seem to be "exact same machine code", that seems to be a false statement. Thank you for your comments overall, has been helpful. $\endgroup$
    – user52174
    Jul 18, 2022 at 22:40
  • $\begingroup$ @user52174 I'm trying to make the point that the byte B8 is totally indistinguishable from an instruction called mov EAX, [EIP++] or mov EAX, next 4 bytes from EIP. Since that instruction isn't actually in the manuals, we have to make up a name for it. If you really wanted, you could make an assembler where the instruction mov EAX, [EIP++] translates to B8 $\endgroup$
    – user253751
    Jul 18, 2022 at 23:10

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