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The "Hack CPU" (Wikipedia/Hack_computer) is a theoretical computer design created by Noam Nisan and Shimon Schocken and described in their book and also used in their Coursera course Nand2Tetris, and in the game https://nandgame.com. Their CPU only has two registers, A and D. Both registers are loaded via the output of the ALU. When loading data from memory to either the A or D register, it has to first pass through the ALU. The A register can also be loaded directly from an instruction, and it also holds the addresses used when accessing memory.

This design surprises me a bit since it seems very slow to have to pass through ALU to load the registers. I am interested in if there is any smart rationale behind the design, and if there are real-world examples of CPUs with similar design? Was the design for example common in the early days of computers? Both questions sort of tell me the same thing: is the design any good, or is it just something more like "educational fiction".

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Some more context to their "Hack computer", it uses Harvard architecture.

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Yes, most CPUs(*) have an accumulator-based architecture. In fact, most CPUs have the very simplest kind of accumulator-based architecture, the kind used in the "Hack CPU", with an accumulator that can only be loaded from the ALU, and whose output can only go back into the ALU, and one input of the ALU connected only to the accumulator. (The D register is the accumulator of the Nand2Tetris "Hack CPU").

it seems very slow to have to pass through ALU to load the registers.

Some accumulator-based processors do have additional connections that can read out the accumulator directly or write to the accumulator directly or both, bypassing the ALU. But routing through the ALU (for example, by zeroing one of the inputs and performing an OR operation) does not add significant delay to LOAD or STORE. Leaving out those additional connections generally reduces transistor count and area, simplifies wiring, and so reduces cost. (thanks, Paul A. Clayton).

An integer ALU is completely combinational logic, producing outputs very quickly after new inputs are applied -- less than a clock cycle. So loading a value from memory into the accumulator (which requires passing that data through the ALU), or writing the value in the accumulator out to memory (which also requires passing that data through the ALU) is not any slower than the register file (completely bypassing the ALU) used in more recent CPUs. Both architectures can be designed to take a single memory cycle for a LOAD or a STORE. (The register file does makes some other kinds of instructions run faster).

real-world examples of CPUs with similar design?

  • As you can see from any PIC microcontroller architecture block diagram, 8-bit PIC microcontrollers have an accumulator called the "W register" connected exactly the same way.
  • The 8085 has an accumulator: "the only way to put a value into the accumulator is through the ALU." -- "Ken Shirriff: Reverse-engineering the 8085's ALU", but it has additional connections to to the ALU that bypass the accumulator. (thanks, user52174)
  • The Intel MCS-51 architecture ("8051" and "8031") has historically been popular. Although Intel no longer sells chips with this architecture, lots of other chips with this architecture are still in production. The MCS-51 also has only a single accumulator, although the 8051 / 8031 architecture block diagram shows more complicated and flexible connections.
  • The PDP-8 architecture has only a single accumulator. (FIXME: link to diagram).
  • The MOS 6502 (still in production as the Western Design Center 6502) has only a single accumulator. (FIXME: link to diagram).
  • The Hitachi 6301 had two accumulators.

(*) In particular, since 2013 Microchip has been shipping a billion CPU chips every year. Most of them are 8-bit PIC microcontrollers with a traditional accumulator-based architecture.

Chips that include the Western Design Center 6502 ship "over a hundred million units per year".

You may be more familiar with computers that have a register file, with many registers that are all more-or-less equally connected to the ALU. In particular, you may be familiar with the x86 architecture (although many people call all of those ALU-connected registers "accumulators", and sometimes call one of those registers "the accumulator"). Since 2020, the number of x86 architecture CPU chips shipped (combined from all manufacturers) is about 350 million per year, so many people incorrectly think it's the top seller, but other CPU architectures sell even more chips per year.

common in the early days of computers?

As far as I can tell, the accumulator-based architecture is still more common in terms of CPUs shipped per year than any other CPU architecture. (It was also common in the early days of computers).

is the design any good

That's a matter of opinion. Some people can't stand it. Other people love it and say there are still categories where it is "the best". But I would hesitate to call an architecture "bad" when it currently outsells (in terms of CPUs sold per year) all x86 CPUs from all manufacturers combined.

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  • $\begingroup$ An accumulator architecture could have an implementation that bypassed the ALU (rather that controlling the ALU function to output the appropriate source), cf. 8051's "more complicated and flexible connections". The ALU's function selection could also bypass the operand around the computational logic rather than, e.g., zeroing one of the inputs and performing an OR operation. As the answer notes, routing through the ALU does not add significant delay (and could reduce transistor count and simplify wiring, reducing area). I suspect educational reasons dominate for Hack. $\endgroup$
    – user4577
    Jul 23, 2022 at 20:43
  • $\begingroup$ @PaulA.Clayton Thanks. I also suspect educational reasons dominate Hack. Really loved nandgame.com but I got the feeling that it would be better to try and work with some real CPUs. $\endgroup$
    – user52174
    Jul 24, 2022 at 1:50
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    $\begingroup$ @David Cary Thanks for answer. I was looking at "accumulator machines" while trying to answer my question, but could not make up my mind if Hack was that. Having read more, accumulator machines seem to be defined by/designed for one address instructions. Hack seems to be more of a two address instruction format. Your answer was helpful, spent all day studying to understand this (incl. managing to model propagation delay in Logisim to be able to write ALU output back into one input register at rising edge of clock. ) $\endgroup$
    – user52174
    Jul 24, 2022 at 2:28
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    $\begingroup$ @PaulA.Clayton Also thanks for mentioning the OR 0 operation. Ken Shirriff mentions the same about the 8085 loading the accumulator only via the ALU output, "You might expect that if you load a value into the accumulator, it would go directly from the data bus to the accumulator. Instead, the value is OR'd with 0 in the ALU and the result is stored in the accumulator. " righto.com/2013/07/reverse-engineering-8085s-alu-and-its.html $\endgroup$
    – user52174
    Jul 24, 2022 at 2:30

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