I'm doing an exercise about the MIPS pipeline with the following characteristics:
-Branches and Branch targets are calculated in the E-stage. -There is forward logic from the output to the input of the E-stage. -You can read an operand from the register file only the cycle after it has been written to it.
The task is to create a diagram for the instructions passing through the cycles. Stalls are marked with X and the aim is to mark the current stage for the instruction with F,D,E,M,WB, or X at that cycle.
This is the code I'm making the diagram for, I don't understand why there are two stalls (X) on the third instruction. Should it not be F X X X D given that the forwarding is from WB to D?
This task is from the course EDA333 given at Chalmers.