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I'm doing an exercise about the MIPS pipeline with the following characteristics:

-Branches and Branch targets are calculated in the E-stage. -There is forward logic from the output to the input of the E-stage. -You can read an operand from the register file only the cycle after it has been written to it.

The task is to create a diagram for the instructions passing through the cycles. Stalls are marked with X and the aim is to mark the current stage for the instruction with F,D,E,M,WB, or X at that cycle.

This is the code I'm making the diagram for, I don't understand why there are two stalls (X) on the third instruction. Should it not be F X X X D given that the forwarding is from WB to D?

This task is from the course EDA333 given at Chalmers.

code diagram

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    – D.W.
    Aug 11, 2022 at 21:18
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    – D.W.
    Aug 11, 2022 at 21:18
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    – begin
    Aug 11, 2022 at 21:25

1 Answer 1

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How could the add instruction stall before it has been decoded (D)? At that point, it is not known that there is a data hazard via $t2 so no stall is possible. So the correct sequence is:

F D stall stall stall E M W

Afaict, three stall cycles are required because "You can read an operand from the register file only the cycle after it has been written to it." But usually in exercises about the MIPS pipeline you are allowed to read and write the same register in the same cycle.

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