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What happens if Operand Fetch and Write Back happen in same cycle?

  • $\begingroup$ By all logic, the CPU shall execute the read and the write sequentially, but in an order such that the result is the same as without pipelining. $\endgroup$
    – user16034
    Commented Nov 2, 2022 at 12:50

2 Answers 2


To avoid contention(hazard) between the 2 stages, a split cache i.e. I-cache(instruction cache) and a D-cache(data cache) is used. Consequently, Fetch and Writeback operations are handled by I and D cache respectively.

  • $\begingroup$ But it changes nothing? What if I need to use D-Cache twice at the same time? $\endgroup$ Commented Nov 2, 2022 at 10:04
  • $\begingroup$ Then you stall(or resolve it by employing a suitable solution), the split cache is being used so that instructions and data can be fetched simultaneously bypassing the von neumann bottleneck. This is an optimisation and not a technique to resolve pipeline hazards. $\endgroup$
    – Rinkesh P
    Commented Nov 2, 2022 at 10:42
  • $\begingroup$ Ok, so two data cache accesses are not possible at same time $\endgroup$ Commented Nov 2, 2022 at 11:11
  • $\begingroup$ Not in a simple processor. More complex processors have no problems. There may be restrictions that both accesses have to go to the same cache line, or to different cache lines, or not overlapping and so on. It depends on how much money you want to spend for more performance. Separate data and instruction cache is a much simpler (cheaper) solution. If you want one instruction cache and two data cache accesses at the same time, you make the data/instruction cache split, and spend the money to have two data accesses at the same time. $\endgroup$
    – gnasher729
    Commented Nov 2, 2022 at 13:56
  • 1
    $\begingroup$ Data fetch is certainly not handled by I-cache. Only instruction fetch is handled by I-cache. $\endgroup$ Commented Nov 2, 2022 at 16:09

It depends on the processor design.

In the most simple solution, a pipeline bubble is inserted. The read (because it's earlier in the pipeline) has to wait until the next cycle after the write is done.

In a more complex processor with a cache, the cache may be able to process multiple read and write requests at the same time. In a design with a cache, both the read and write must be prepared to wait anyway, in case the cache line is not present in the cache.


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