What happens if Operand Fetch and Write Back happen in same cycle?
To avoid contention(hazard) between the 2 stages, a split cache i.e. I-cache(instruction cache) and a D-cache(data cache) is used. Consequently, Fetch and Writeback operations are handled by I and D cache respectively.
It depends on the processor design.
In the most simple solution, a pipeline bubble is inserted. The read (because it's earlier in the pipeline) has to wait until the next cycle after the write is done.
In a more complex processor with a cache, the cache may be able to process multiple read and write requests at the same time. In a design with a cache, both the read and write must be prepared to wait anyway, in case the cache line is not present in the cache.