I've recently learnt the execution of MIPS instruction set using single cycle processor. However I'm not getting one thing. Since one clock cycle is needed for the complete instruction we only have one positive clock edge. When the clock is made high on the first time in this rising PC value is written but we may have other write operations also like Reg Write or Mem Write. But the rising edge is gone and we've to wait for the next cycle to write. So how in one cycle both writes are possible for a single instruction ?
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A single clock signal can trigger many, many independent actions. And the processor is pipelined, which means in one cycle it will execute different parts of different instructions.
