I have a computer architecture exam tomorrow and my professor gave us some questions for practice. I just need to clear some confusions.

The first question is:
"a) In a Direct-Mapped Cache, modify the following Page-to-Cache address translation circuitry (attached with the post) if the Page Capacity is 1 KiWords and Cache Capacity is 32 Words. Determine the width of Tag, Set, Valid bit, and Data fields.
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b) How many memory locations from the Page will be mapped to each of the 32 sets?

c) Calculate C (cache capacity), B (blocks), b (block size), N (number of blocks in a set), S (number of sets)? Is the information enough to calculate these?"

We are following the book "Digital Design and Computer Architecture (RISC-V edition)" by Sarah Harris, David Harris for the course. After having read through the book, what doesn't make sense to me is why (and how?) are we mapping pages to cache? Don't we just map main memory addresses to cache? I am pretty lost here so any help will be appreciated since my exam is tomorrow and I really need to figure this question out.




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