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How to go about analysing the I/O complexity when there are multiple levels of memory involved? Looking up I/O complexity analyses returns papers such as this one, which generally assume for simplicity that the memory is just two-level (disk and cache).

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  • $\begingroup$ What memory levels do you mean? $\endgroup$
    – Bulat
    Jun 3 at 14:27
  • $\begingroup$ Anything over two-level. Looking for pointers to analyses of I/O complexities with >2 levels. (Most machines I've used are 3 cache levels + DRAM + disk, for instance, but I'm not looking for analyses of any particular kinds of hierarchies) $\endgroup$
    – William Edwardson
    Jun 4 at 22:22
  • $\begingroup$ oh, you mean cpu caches. I/O devices, or rather DMA engines, can't access CPU caches, so any data to be exchanged is flushed from caches to RAM. $\endgroup$
    – Bulat
    Jun 5 at 2:41

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