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probably a couple decades too late to ask this question, but does anyone know anything/have detailed documentation about the hardware/design underlying the ALU unit in the early MIPS R2000 CPU?

Ideally I am looking for a circuit diagram like the following:

desired example

I don't need/am already familiar with the information from spec sheets/RISC guides like this:

enter image description here

Unless MIPS Computer Systems/R2000 designers have talked about it somewhere, I believe this is a reverse engineering question.

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What you're looking for is unlikely to have ever existed.

The R2000 ALU was almost certainly not designed in terms of gates, but either in a high-level synthesis language such as Verilog, or in terms of individual transistors.

John Hennessy, the main designer and one of the founders of MIPS, co-wrote two books on the subject. His co-author was David Patterson, who led the Berkeley RISC project that became the SPARC architecture.

The books are:

  • Patterson, David; Hennessy, John (1996). Computer Architecture: A Quantitative Approach (1st ed.). Morgan Kaufmann. ISBN 978-1-55-860329-5.
  • Patterson, David; Hennessy, John (1994). Computer Organization and Design (1st ed.). Morgan Kaufmann. ISBN 978-1-55-860281-6.

The latter book introduced the DLX, which is essentially a modernisation and clean-up of the MIPS I, and has much more detailed diagrams and explanations of the data path.

DLX pipeline diagram from Computer Organization and Design (1st ed)

And an extended discussion, with many diagrams, of how to handle issues such as hazard detection and forwarding.

DLX block diagram with forwarding

Needless to say, both books are worth your time to read, the latter one especially.

But, of course, you're asking about the ALU.

It's likely to be a lot simpler than you might think. Chapter 4 of Computer Organization and Design describes the DLX ALU, which is probably pretty much the same as the MIPS I integer ALU. It's made from a bunch of 1-bit ALUs which compute all of the interesting operations in parallel, followed by a multiplexer to select which one is to be computed.

DLX 1-bit ALU

The high-bit ALU is slightly modified with some additional circuitry to perform overflow detection. And so the ALU as a whole looks like this.

DLX 32-bit ALU

And that is probably as close as you're going to get.

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  • $\begingroup$ cheers. we're working through the latter text in class right now. my question sort of prompted by the pseudo-superscalar behavior of the Z80's ALU design seen in youtube.com/watch?v=aHx-XUA6f9g&t=320s $\endgroup$
    – shea
    Commented Aug 25, 2023 at 3:23
  • $\begingroup$ @Shea You'll probably enjoy this site. visual6502.org Note that the R2000 was CMOS, which uses almost double the transistors of an earlier nMOS design like Z80 or 6502, so a true circuit diagram of the R2000 is probably going to look much more complicated. But it's broadly similar in that CMOS VLSI circuits are mostly made out of inverting gates: usually NAND, NOR, and NOT. For some non-monotonic "gates" such as adders, designers sometimes use more complex transistor logic followed by an inverting buffer so that it behaves like an inverting gate. $\endgroup$
    – Pseudonym
    Commented Aug 25, 2023 at 3:33
  • $\begingroup$ also check out this site: righto.com/2021/02/a-one-bit-processor-explained-reverse.html - it contains articles about Z80 and ARM1 internals too $\endgroup$
    – Bulat
    Commented Aug 26, 2023 at 10:49

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