I'm reading a text book on CPU architecture and I have something that confuses me: The text book defines 4 different instruction execution models in CPUs, Stack (where a CPU only has a stack and is able to perform operations on the first and second elements of the stack and push the result back), Accumulator (the CPU loads a value from the memory and add it to the current accumulated value), Register-Memory (where a CPU has a regiser and performs operations on values from both the memory and the register), Register-register (where a CPU performs operations on values that are only stored in the register). Each execution model has a different format of instructions, my question is, which of these models is used by the RISC-V architecture? because it seems to be, when looking at the RISC-V ISA, that it does all of the above.


1 Answer 1


In the terminology that you're using, RISC-V is a register-register ISA.

For integer and floating point instructions:

  • All arithmetic and logic operations take registers as operands and write the result to a register.
  • The only operations that access memory are load and store operations.
  • There is no dedicated accumulator register.
  • There is no dedicated stack pointer register. The ABI might specify one, but the hardware does not.

While they are not all requirements, together they imply a register-register ISA.

There is one main exception: The RISC-V "A" extension supports atomic read/modify/write memory operations (e.g. atomic swap, atomic add, etc).


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.