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Consider a very simple RAM chip that has 20 address pins and 4 data pins. I would like to know the function of the 4 data pins when only 1 data pin is enough.

What do I mean by 1 data pin is enough? If an address is applied to address pins, a memory cell is selected (which can only have value 0 or 1 — in a very basic RAM). Isn't it counter-intuitive to send 0 bit using 4 data pins when 1 data pin is okay. So why would the RAM have 4 data pins in this case?

If it's a memory system that combines multiple RAM chips, I understand having multiple data pins but I don't understand it for a single RAM chip

NB: Something might be missing from my base understanding because I've been struggling to understand how 4 data pins are necessary.

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  • $\begingroup$ Who gets to define the width of, say, an ALU? Who gets to define the width of of the ports of a RAM device? What's the difference between 1 Mbit devices $2^{20}\times 1$ and $2^{19}\times 2$ when needing a memory of a) $2^{19}\times 27$ bits b) $2^{20}\times 27$ bits? $\endgroup$
    – greybeard
    Sep 10, 2023 at 6:17
  • $\begingroup$ Obviously, this RAM stores 4 bits (a nibble) at every address. In total, $2^{20}\times 4$ bits. $\endgroup$
    – user16034
    Sep 12, 2023 at 9:28

1 Answer 1

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Each address in this RAM chip stores 4 bits. For example, you can write data 0100 to address 01010101010101010101 and then write data 0011 to address 00000000001111111111 and then read address 01010101010101010101 and you get the data 0100 again.

You can view it as 4 1-bit RAM chips in parallel. Each address selects a group of 4 memory cells.

Each address has a separate 4 bits. It does not read 4 addresses at once. The second data bit from the first address is not the first data bit from the second address.


If you want 8-bit memory, you can combine 8 1-bit chips like you said, or you can use 2 4-bit chips, or 1 8-bit chip, and the circuit designer usually finds it more convenient and cheaper if there are less chips.

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  • $\begingroup$ On the topic of circuit design, physical layout is also a concern. Modern busses are so fast that we have to take into account the physical length of conductors on a circuit board to ensure that some bits don't arrive significantly later than others, a phenomenon known as "clock skew". Most modern high-speed peripherals these days are serial for this reason. Modern DRAM modules act more like peripherals than they used to. $\endgroup$
    – Pseudonym
    Sep 12, 2023 at 5:23
  • $\begingroup$ @user253751. Are you saying a memory cell saves 4 bits? I thought memory cells were supposed to be 0 or 1? $\endgroup$
    – Bazzan
    Sep 14, 2023 at 20:12
  • $\begingroup$ @Bazzan think of 4 memory cells next to each other; the whole set of 4 shares the same address, but each one is connected to a different data pin $\endgroup$ Sep 15, 2023 at 10:16
  • $\begingroup$ @user253751, from Duntemann's Assembly step by step book, this diagram shows that an adress picks only one memory cell $\endgroup$
    – Bazzan
    Sep 15, 2023 at 18:49
  • $\begingroup$ Basically, I should know that an address in a single RAM chip can have more than 1 bit? Is this because of the MLC/QLC (memory cell being able to store more than 1 bit) concept I've been seeing or something else entirely? $\endgroup$
    – Bazzan
    Sep 15, 2023 at 19:59

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