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In the Computer organization and design book, there is an exercise in chapter 1 that stated:

Assume that, as the program is parallelized to run over multiple cores, the number of arithmetic and load/store instructions per processor is divided by 0.7 × p (where p is the number of processors) but the number of branch instructions per processor remains the same.

My question is: While other instructions reduce as the number of processors are increased, why does the number of branch instructions per processor remain the same? Is it true in practice or this question is about an imaginary CPU?

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This is very curious, and I would think someone is really misunderstanding something quite badly.

There is hyperthreading, where one core basically handles two instruction streams, without any execution units being added. The total performance for two threads will be closer to the theoretical maximum of instructions that this core could achieve. If you have incredibly good code that gets 80% of the theoretical performance it might go up to 90%. Bad code getting only 30% of the theoretical maximum might go to 60%. It is cheap to do and may or may not improve performance.

But beyond that, you will have n independent CPUs. They will usually be able to perform n times the instructions. Both branches, integer, floating point, and vector instructions.

The only problem you will have is that the hardware for accessing RAM will only exist once. You can bet that this hardware is as efficient as possible. On my personal computer, eight cores cannot use all available bandwidth. Another problem is that some caches will be shared. On my system, there is 24MB of L2 cache, with 12 MB each available to a group of 4 cores. So if two cores are used, one from each group of four, they have 12 MB each. If you use all eight cores, they have 3MB each on average. But that will not cause a slowdown like the one you were told about.

AMD is now building a monstrosity with 64 cores. According to your information that would only be able to perform about 40% more instructions than a single core. Somehow I think AMD ignored that information you were given and built their own reality.

A multi-core processor with p cores where the number of operations per core is divided by 0.7p would be impossible to sell.

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  • $\begingroup$ I wonder what computer you have? And how do you check that 8 cores don't use the entire bandwidth? How do you define bandwidth? No computer can reach 100% of theoretical RAM bandwidth due to the complexities of the real world. $\endgroup$
    – Bulat
    Oct 20, 2023 at 21:10
  • $\begingroup$ Just an ordinary 8 core M1 that you can buy in any store for not very much money. Bandwidth is I think 200 GB/sec (more expensive models have 400 or 800 GB/sec), and you just can't issue enough load/store instructions for that with the CPU alone. Need to use the GPU as well. It's eight byte per core per cycle. $\endgroup$
    – gnasher729
    Oct 21, 2023 at 17:52
  • $\begingroup$ How do I check? Measuring. $\endgroup$
    – gnasher729
    Oct 21, 2023 at 17:53
  • $\begingroup$ you can measure any cpu and find that they are never 100% efficient at using RAM bandwidth. as of M1 pro/max, it definitely has RAM tuned for GPU, but still one CPU core can issue multiple load operations per cycle (even weaker ARM A7xx cores can), and M1 should support at least 128-bit Neon. Note that M1 ultra has more CPU cores (it's essentially two Max chips glued together). $\endgroup$
    – Bulat
    Oct 22, 2023 at 18:05

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