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While searching for the structure of the MMU, I found the image below (80386 Internal Architecture).

I have three questions.

Q1. I'd like to know the roles of 'Adder', 'Page Cache', and 'Control and Attribute PLA'.

I found some description for 'Control and Attribute PLA' (link below), but I still can't understand it. https://www.pcpolytechnic.com/entc/pdf/architecture%20pdf.pdf

"The control and attribute PLA checks the privileges at the page level."

Q2. Does Modern CPU MMU (like the Intel core series) use a structure similar to 80386 MMU?

Q3. If not, How is it structured?

80386

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  • $\begingroup$ Welcome to CS.SE! In the future please ask only one question per post. Thank you! $\endgroup$
    – D.W.
    Commented Nov 8, 2023 at 3:01

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That's three questions, but I'll try my best. I looked at other techincal papers about the i386, and this is my best guess.

1. I'd like to know the roles of 'Adder', 'Page Cache', and 'Control and Attribute PLA'.

I can't work out why there's an adder in the paging unit. It's not needed in the i386 to calculate page table entries or the final physical address because everything can be done with simple wiring.

I'm 99% sure that the "page cache" is what would, in more customary terminology, be called a Translation Lookaside Buffer. The purpose is to cache page table entries so that the CPU does not need to traverse the page table structure on every memory access.

A PLA is one way to design combinational circuits. The main job of the PLA is presumably to ensure that the memory access is not a page fault, such as if the instruction attempts to write to a read-only page.

Q2. Does Modern CPU MMU (like the Intel core series) use a structure similar to 80386 MMU?

Surprisingly, yes. There are a few differences for the modern era, such as:

  • Support for large pages, and larger physical memories (e.g. PAE).
  • Support for 64-bit addressing. In 64 bit mode (called "long mode" in Intel-speak), some of the 286 and 386-era protection mechanisms are not supported, and neither is segmentation.
  • Support for process context identifiers (PCID). The idea is that TLB entries can be tagged with the process id that they belong to, so that the TLB does not need to be flushed on every context switch.
  • Instructions (and hardware to support them) to selectively invalidate individual TLB entries. This is required to support virtual memory coherency among multiple CPUs.

This complicates the control logic, but the overall structure is quite similar.

Non-Intel CPUs don't always work the same way, however. MIPS and Alpha, for example, have a software-managed TLB, so that operating systems can implement their own cache policies. But you specifically asked about Intel/AMD/etc, so that's not relevant here.

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