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If a CPU is able to execute multiple instructions in parallel, and fetching/decoding/scheduling instructions happen in batches, and there's multiple execution units, etc. What does the IP register points to among all the instructions being executed at the same time?

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When you read about the instruction set of a processor, in order not to blow up the brain of the reader, we pretend that instructions are executed one after the other. AND whatever the processor does, it acts AS IF that’s how it works.

In reality there are multiple different states related to the IP. There is an instruction reader that reads instructions fro memory. It has a next instruction to read, and probably reads many instructions in one go. Then you have an instruction decoder which decodes instructions and determines where each one starts (simple on an ARM processor where each instruction is four bytes, difficult on x86 where each instruction is 1 to 15 bytes. Anyway, at this point you have several instructions and know where each starts.

There are many other stages, each keeping track of instructions and their addresses. The last stage is the retire stage. If an instruction sets a register of memory cell, the instruction is retired when the results are moved to this location. When an instruction is retired, that’s the point where we can say it has been executed.

You could take the instruction that is the next one to be retired as “the instruction pointer”. If something interrupts your processor, it can throw away what it was working on and start over from the address of the first unretirrd instruction.

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  • $\begingroup$ Thinking on the "IP is the address of the last retired instruction + 1" idea, since a CPU can decode more than one instruction per-cycle because of its multiscalar nature, does it mean that the instruction pointer can grow faster than +1 per cycle (for example in a a sequential blob of instructions without jumps or loops)? $\endgroup$
    – ABu
    Nov 25, 2023 at 22:48

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