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I've been reading the book "A Primer on Memory Consistency and Cache Coherency", and it contains the following paragraph:

The Atomic Requests property states that a coherence request is ordered in the same cycle that it is issued. This property eliminates the possibility of a block’s state changing—due to another core’s coherence request—between when a request is issued and when it is ordered. The Atomic Transactions property states that coherence transactions are atomic in that a subsequent request for the same block may not appear on the bus until after the first transaction completes (i.e., until after the response has appeared on the bus).

I'm trying to understand what this means in practice, since I'm not very familiar with how buses typically operate. Let's assume we have two cores that on the same clock cycle wants to access memory address A. In other words, both try to issue a coherence request for A on the same cycle. Let's assume the cache controller of core 1 manages to make its request.

What happens then during the next clock cycle? Core 2 is not allowed to post the request that it wants, since the first transaction by the first core is still waiting for a response (atomic transactions). How is the cache controller on core 2 aware of this? Or does it at the start of the next clock cycle already see the coherence request from core 1 in the previous one, so that it knows to wait until it sees the response on the wire? Or is the bus somehow tracking pending requests and denying core 2 from making the request?

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