0
$\begingroup$

I'm studying for final and currently stuck in the question below.

You have an embedded processor. It has its L1 instruction and data cache. No L2 or last level cache are available. Consider the following assumptions. The processor core is running at 2 GHz.

  • Memory access instructions are 25 % of total instructions.
  • Reads or writes account for 50 % of memory instructions each.
  • Instruction cache miss rate is 2 % while data cache miss rate is 5%.
  • Data cache is a write-through cache with the write allocate policy.
  • Block size of the cache is 64 bytes.
  • A whole block is written to the memory upon a write hit.

Calculate the memory bandwidth to support the data cache (in bytes/sec).

My solution1:

Read Hit: 0 access -> 0.95 * 0.5

Read Miss: 1 access -> 0.05 * 0.5

Write Hit: 1 access -> 0.95 * 0.5

Write Miss: 2 access -> 0.05 * 0.5

-> 2 * 10^9 x 0.25 x (0 * 0.95 * 0.5 + 1 * 0.05 * 0.5 + 1 * 0.95 * 0.5 + 2 * 0.05 * 0.5) x 64 = 17.6 * 10^9 bytes / sec

My solution2:

-> 2 * 10^9 x 0.25 x 0.05 x 64 = 1.6 * 10^9 bytes / sec

I want to know which one is right and the reason. Can I get some help?

$\endgroup$
1
  • $\begingroup$ Where did 0 access, 1 access, 1 access, 2 access come from? $\endgroup$ Commented Jan 14 at 15:39

0

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Browse other questions tagged or ask your own question.